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LTC1644IGN

CompactPCI Bus Hot Swap Controller

Linear Technology 

LTC1644

PI FU CTIO S

OFF/ON (Pin 5): Digital Input. Connect the CPCI BD_SEL#

signal to the OFF/ON pin. When the OFF/ON pin is pulled

low, the GATE pin is pulled high by a 65µA current source

and the internal 12V and –12V switches are turned on.

When the OFF/ON pin is pulled high, the GATE pin will be

pulled to ground by a 225µA current source and the 12V

and –12V switches turn off.

The OFF/ON pin is also used to reset the electronic circuit

breaker. If the OFF/ON pin is cycled high and low following

the trip of the circuit breaker, the circuit breaker is reset

and a normal power-up sequence will occur.

FAULT (Pin 6): Open-Drain Digital I/O. FAULT is pulled low

when a current limit fault is detected. Current limit faults

are ignored until the voltage at the TIMER pin is within 1V

of 12VIN. Once the TIMER cycle is complete, FAULT will

pull low and the chip latches off in the event of an

overcurrent fault. The chip will remain latched in the off

state until the OFF/ON pin is cycled high then low.

Forcing the FAULT pin low with an external pull-down will

cause the chip to be latched into the off state after a 45µs

deglitching time.

PWRGD (Pin 7): Open-Drain Digital Power Good Output.

Connect the CPCI HEALTHY# signal to the PWRGD pin.

PWRGD remains low while V12VOUT ≥ 11.1V, V3VOUT ≥

2.9V, V5VOUT ≥ 4.62V and VEEOUT ≤ –10.5V. When any of

the supplies falls below its power good threshold voltage,

PWRGD will go high after a 10µs deglitching time.

GND (Pin 8): Chip Ground.

RESETIN (Pin 9): Digital Input. Connect the CPCI PCI_RST#

signal to the RESETIN pin. Pulling RESETIN low will cause

RESETOUT to pull low.

RESETOUT (Pin 10): Open-Drain Digital Output. Connect

the CPCI LOCAL_PCI_RST# signal to the RESETOUT pin.

RESETOUT is the logical combination of RESETIN and

PWRGD.

DRIVE (Pin 11): Precharge Base Drive Output. Provides

base drive for an external NPN emitter-follower which in

turn biases the PRECHARGE node.

PRECHARGE (Pin 12): Precharge Monitor Input. An on-

chip error amplifier servos the DRIVE pin voltage to keep

the precharge node at 1V.

5VIN (Pin 13): 5V Supply Sense Input. An undervoltage

lockout circuit prevents the switches from turning on

when the voltage at the 5VIN pin is less than 2.48V. If no

5V input supply is available, tie the 5VIN to the 3VIN pin.

5VSENSE (Pin 14): 5V Current Limit Sense. With a sense

resistor placed in the supply path between 5VIN and

5VSENSE, the GATE pin voltage will be adjusted to maintain

a constant 51mV across the sense resistor and a constant

current through the switch while the TIMER pin is low. A

foldback feature reduces the current limit as the voltage at

the 5VOUT pin approaches GND.

When the TIMER pin is high, the circuit breaker function is

enabled. If the voltage across the sense resistor exceeds

55mV but is less than 150mV, the circuit breaker is tripped

after a 45µs time delay. In the event the sense resistor

voltage exceeds 150mV, the circuit breaker trips immedi-

ately and the chip latches off. To disable the current limit,

5VSENSE and 5VIN can be shorted together.

GATE (Pin 15): High Side Gate Drive for the External 3.3V

and 5V N-Channels pass transistors. Requires an external

series RC network to compensate the current limit loop

and set the minimum ramp-up rate. During power up, the

slope of the voltage rise at the GATE is set by the 65µA

current source connected to 12VIN and the external ca-

pacitor connected to GND (C1, see Figure 1) or by the 3.3V

or 5V current limit and the bulk capacitance on the 3VOUT

or 5VOUT supply lines (CLOAD(5VOUT) or CLOAD(3VOUT), see

Figure␣ 1). During power down, the slew rate of the GATE

voltage is set by the 225µA current source connected to

GND and the external GATE capacitor (C1, see Figure 1).

The voltage at the GATE pin will be modulated to maintain

a constant current when either the 3V or 5V supplies go

into current limit while the TIMER pin is low. In the event

of a fault or an undervoltage condition, the GATE pin is

immediately pulled to GND.

3VSENSE (Pin 16): 3.3V Current Limit Set. With a sense

resistor placed in the supply path between 3VIN and

3VSENSE, the GATE pin voltage will be adjusted to maintain

a constant 51mV across the sense resistor and a constant

current through the switch while the TIMER pin is low. A

foldback feature reduces the current limit as the voltage at

the 3VOUT pin approaches GND.

1644f

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