LTC1608AIG Просмотр технического описания (PDF) - Linear Technology
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LTC1608AIG Datasheet PDF : 20 Pages
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W
FU CTIO AL BLOCK DIAGRA
+
22µF
DIFFERENTIAL
ANALOG INPUT
± 2.5V
2.2µF
3
VREF
10µF
5V 10µF
10Ω
+
36
35
AVDD AVDD
4 REFCOMP
4.375V
1.75X
7.5k 2.5V
REF
5V 10µF
+
9
10
DVDD
DGND
SHDN 33
CONTROL
LOGIC
AND
TIMING
CS 32
CONVST 31
RD 30
BUSY 27
µP
CONTROL
LINES
1 AIN+
2 AIN–
16-BIT
SAMPLING
ADC
B15 TO B0
OUTPUT
BUFFERS
AGND AGND AGND AGND VSS
5
6
7
8 34
OVDD 29
OGND 28
5V OR
3V
10µF
D15 TO D0
16-BIT
PARALLEL
BUS
11 TO 26
1608 BD
+ 10µF
–5V
LTC1608
TEST CIRCUITS
Load Circuits for Access Timing
DN
1k
CL
5V
1k
DN
CL
(A) Hi-Z TO VOH AND VOL TO VOH
(B) Hi-Z TO VOL AND VOH TO VOL
1608 TC01
Load Circuits for Output Float Delay
DN
1k
CL
5V
1k
DN
CL
(A) VOH TO Hi-Z
(B) VOL TO Hi-Z
1608 TC02
APPLICATIO S I FOR ATIO
CONVERSION DETAILS
The LTC1608 uses a successive approximation algorithm
and internal sample-and-hold circuit to convert an analog
signal to a 16-bit parallel output. The ADC is complete with
a sample-and-hold, a precision reference and an internal
clock. The control logic provides easy interface to micro-
processors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion, the successive
approximation register (SAR) resets. Once a conversion
cycle has begun, it cannot be restarted.
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from the
Most Significant Bit (MSB) to the Least Significant Bit
(LSB). Referring to Figure 1, the AIN+ and AIN– inputs are
acquired during the acquire phase and the comparator
offset is nulled by the zeroing switches. In this acquire
phase, a duration of 480ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
During the convert phase, the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the CSMPL capacitors to ground,
transferring the differential analog input charge onto the
summing junctions. This input charge is successively
7
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