LTC1451 Просмотр технического описания (PDF) - Linear Technology

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LTC1451

12-Bit Rail-to-Rail Micropower DACs in SO-8

Linear Technology 

LTC1451

LTC1452/LTC1453

PI FU CTIO S

CLK: The TTL Level Input for the Serial Interface Clock.

DIN: The TTL Level Input for the Serial Interface Data. Data

on the DIN pin is latched into the shift register on the rising

edge of the serial clock.

CS/ LD: The TTL Level Input for the Serial Interface Enable

and Load Control. When CS/LD is low the CLK signal is

enabled, so the data can be clocked in. When CS/LD is

pulled high, data is loaded from the shift register into the

DAC register, updating the DAC output.

DOUT: The Output of the Shift Register which Becomes

Valid on the Rising Edge of the Serial Clock.

GND: Ground.

REF: The Output of the Internal Reference and the Input

to the DAC Resistor Ladder. An external reference with

voltage up to VCC/2 may be used for the LTC1452.

VOUT: The Buffered DAC Output.

VCC: The Positive Supply Input. 4.5V ≤ VCC ≤ 5.5V

(LTC1451), 2.7 ≤ VCC ≤ 5.5V (LTC1452/LTC1453). Re-

quires a bypass capacitor to ground.

BLOCK DIAGRA

CLK 1

DIN 2

CS/LD 3

DOUT 4

12-BIT

SHIFT

REGISTER

LD

DAC

REGISTER

12-BIT DAC

POWER-ON

RESET

REFERENCE

LTC1451: 2.048V

LTC1453: 1.22V

WU

W

TI I G DIAGRA

CLK

t9

DIN

B0

PREVIOUS WORD

t1

t2

B11

MSB

t4

B10

CS/LD

t8

8 VCC

+

7 VOUT

–

6 REF

5 GND

11451/2/3 BD

t6

t7

t3

B1

B0

LSB

t5

DOUT

6

B11

PREVIOUS WORD

B10

B1

B11

B0

CURRENT WORD

1451/2/3 TD

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