LTC1421(Rev_A) Просмотр технического описания (PDF) - Linear Technology

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Компоненты Описание

производитель

LTC1421
(Rev.:Rev_A)

Hot Swap Controller

Linear Technology 

LTC1421/LTC1421-2.5

APPLICATIONS INFORMATION

When VCCLO collapses, there is enough energy stored on

the 1µF capacitor connected to AUXVCC to keep the gate

discharge circuitry alive long enough to fully turn off the

external N-channels.

Power N-Channel Selection

The RDS(ON) of the external pass transistor must be low

enough so that the voltage drop across it is about 200mV

or less at full current. If the RDS(ON) is too high, the voltage

drop across the transistor might cause the output voltage

to trip the reset circuit. Table 2 lists the transistors that are

recommended for use with the LTC1421.

Table 2. N-Channel Selection Guide

CURRENT

LEVEL (A)

PART

NUMBER

MANUFACTURER

0 to 1

MMDF2N02E

Motorola

1 to 2

MMDF3NO2HD

Motorola

2 to 5

MTB30N06

Motorola

5 to 10

MTB50N06E

Motorola

10 to 20 MTB75N05HD

Motorola

DESCRIPTION

Dual N-Channel SO-8

RDS(ON) = 0.1Ω

Dual N-Channel SO-8

RDS(ON) = 0.09Ω

Single 30A

N-Channel DD Pak

RDS(ON) = 0.05Ω

Single

N-Channel DD Pak

RDS(ON) = 0.025Ω

Single

N-Channel DD Pak

RDS(ON) = 0.0095Ω

Data Bus

When a board is inserted or removed from the host, care

must be given to prevent the system data bus from being

corrupted when the data pins make or break contact. One

problem is that the fully discharged input or output capaci-

tance of the logic gates on the board will draw an inrush

current when the data bus pins first make contact. The

inrush current can temporarily corrupt the data bus, but

usually will not cause long term damage. The problem can

be minimized by insuring the input or output data bus

capacitance is kept as small as possible.

The second, and more serious problem involves the

diodes to VCC at the input and output of most logic families

(Figure 12).

DATA

BUS

VCC

D1

OUT

D2

BACKPLANE

BOARD

1421 F12

Figure 12. Typical Logic Gate Loading the Data Bus

R1

Q1

0.005Ω MTB50N06E

5V

+ C4

VCC

23 22 21 20

2200µF

SYSTEM

DATA BUS

LTC1421

5

DISABLE

GND

12

24

QS3384 VCC

2

3

15

14

5

4

16

17

6

7

BOARD

19

18

DATA BUS

9

8

20

21

10

11

23

22

1

12

GND

13

1421 F13

Figure 13: Buffering the Data Bus

With the board initially unpowered, the VCC input to the

logic gate is at ground potential. When the data bus pins

make contact, the bus line is clamped to ground through

the input diode D1 to VCC. Large amounts of current can

flow through the diode and cause the logic gate to latch up

and destroy itself when the power is finally applied. This

12

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