datasheetbank_Logo
Технический паспорт Поисковая и бесплатно техническое описание Скачать

LT8705 Просмотр технического описания (PDF) - Linear Technology

Номер в каталоге
Компоненты Описание
производитель
LT8705 Datasheet PDF : 44 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LT8705
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, SHDN = 3V unless otherwise noted. (Note 3)
PARAMETER
SYNC High Level for Synchronization
SYNC Low Level for Synchronization
SYNC Clock Pulse Duty Cycle
Recommended Minimum SYNC Ratio fSYNC/fOSC
CLKOUT Output Voltage High
CLKOUT Output Voltage Low
CLKOUT Duty Cycle
CLKOUT Rise Time
CLKOUT Fall Time
CLKOUT Phase Delay
CONDITIONS
VSYNC = 0V to 2V
1mA Out of CLKOUT Pin
1mA Into CLKOUT Pin
TJ = –40°C
TJ = 25°C
TJ = 125°C
CLOAD = 200pF
CLOAD = 200pF
SYNC Rising to CLKOUT Rising, fOSC = 100kHz
MIN TYP MAX UNITS
l 1.3
V
l
0.5
V
20
80
%
3/4
2.3 2.45 2.55
V
25 100
mV
21.4
%
42.5
%
75
%
30
ns
25
ns
l 160 180 200
Deg
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Do not force voltage on the VC pin.
Note 3: The LT8705E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8705I is guaranteed over the full –40°C to 125°C junction temperature
range.
Note 4: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 5: This specification not applicable in the FE38 package.
Note 6: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only, otherwise permanent damage may
occur.
Note 7: Negative voltages on the SW1 and SW2 pins are limited, in an
application, by the body diodes of the external NMOS devices, M2 and
M3, or parallel Schottky diodes when present. The SW1 and SW2 pins
are tolerant of these negative voltages in excess of one diode drop below
ground, guaranteed by design.
8705p
6
For more information www.linear.com/8705

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]