MAX101A Просмотр технического описания (PDF) - Maxim Integrated

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MAX101A

500Msps, 8-Bit ADC with Track/Hold

Maxim Integrated 

500Msps, 8-Bit ADC with Track/Hold

CLK

N–1

N

N+1 N+2

DCLK

0

1

+14 +15 +16 +17

7

8

ADATA

N-1

N+1

N+3

BDATA

tPD2

tPD2

N-2

N

N+2

NOTE: DATA ARBITRARY ON START-UP FOR SIDE A OR B, SEE INTERLEAVING (INPUT CLOCK PHASING) SECTION.

Figure 2. Output Timing, Clock to Data, Normal Mode (DIV10 = OPEN)

CLK

N

N+1 N+2 N+3

+15 +16 +17

DCLK

ADATA

BDATA

N

N+5

NOTE: DATA ARBITRARY ON START-UP FOR SIDE A OR B, SEE INTERLEAVING (INPUT CLOCK PHASING) SECTION.

Figure 3. Output Timing, Test Mode (DIV10 = GND)

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