LM3S6965-IRN20A0T Просмотр технического описания (PDF) - Unspecified
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LM3S6965-IRN20A0T Datasheet PDF : 578 Pages
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LM3S6965 Microcontroller
List of Figures
Figure 1-1. Stellaris® 6000 Series High-Level Block Diagram ............................................................... 29
Figure 2-1. CPU Block Diagram ......................................................................................................... 38
Figure 2-2. TPIU Block Diagram ........................................................................................................ 39
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 49
Figure 5-2. Test Access Port State Machine ....................................................................................... 52
Figure 5-3. IDCODE Register Format ................................................................................................. 57
Figure 5-4. BYPASS Register Format ................................................................................................ 58
Figure 5-5. Boundary Scan Register Format ....................................................................................... 58
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 60
Figure 7-1. Hibernation Module Block Diagram ................................................................................. 121
Figure 8-1. Flash Block Diagram ...................................................................................................... 139
Figure 9-1. GPIO Port Block Diagram ............................................................................................... 164
Figure 9-2. GPIODATA Write Example ............................................................................................. 165
Figure 9-3. GPIODATA Read Example ............................................................................................. 165
Figure 10-1. GPTM Module Block Diagram ........................................................................................ 205
Figure 10-2. 16-Bit Input Edge Count Mode Example .......................................................................... 209
Figure 10-3. 16-Bit Input Edge Time Mode Example ........................................................................... 210
Figure 10-4. 16-Bit PWM Mode Example ............................................................................................ 211
Figure 11-1. WDT Module Block Diagram .......................................................................................... 240
Figure 12-1. ADC Module Block Diagram ........................................................................................... 264
Figure 12-2. Internal Temperature Sensor Characteristic ..................................................................... 267
Figure 13-1. UART Module Block Diagram ......................................................................................... 297
Figure 13-2. UART Character Frame ................................................................................................. 298
Figure 13-3. IrDA Data Modulation ..................................................................................................... 300
Figure 14-1. SSI Module Block Diagram ............................................................................................. 337
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 339
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 340
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 341
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 341
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 342
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 343
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 343
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 344
Figure 14-10. MICROWIRE Frame Format (Single Frame) .................................................................... 345
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 346
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 346
Figure 15-1. I2C Block Diagram ......................................................................................................... 374
Figure 15-2. I2C Bus Configuration .................................................................................................... 375
Figure 15-3. START and STOP Conditions ......................................................................................... 375
Figure 15-4. Complete Data Transfer with a 7-Bit Address ................................................................... 376
Figure 15-5. R/S Bit in First Byte ........................................................................................................ 376
Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 376
Figure 15-7. Master Single SEND ...................................................................................................... 379
Figure 15-8. Master Single RECEIVE ................................................................................................. 380
Figure 15-9. Master Burst SEND ....................................................................................................... 381
November 30, 2007
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