LM3S6965-IQN20A2T Просмотр технического описания (PDF) - Unspecified
Номер в каталоге
Компоненты Описание
производитель
LM3S6965-IQN20A2T Datasheet PDF : 578 Pages
| |||
LM3S6965 Microcontroller
10 General-Purpose Timers ................................................................................................. 204
10.1 Block Diagram ........................................................................................................................ 204
10.2 Functional Description ............................................................................................................. 205
10.2.1 GPTM Reset Conditions .......................................................................................................... 206
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 206
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 207
10.3 Initialization and Configuration ................................................................................................. 211
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 211
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 212
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 212
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 213
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 213
10.3.6 16-Bit PWM Mode ................................................................................................................... 214
10.4 Register Map .......................................................................................................................... 214
10.5 Register Descriptions .............................................................................................................. 215
11 Watchdog Timer ............................................................................................................... 240
11.1 Block Diagram ........................................................................................................................ 240
11.2 Functional Description ............................................................................................................. 240
11.3 Initialization and Configuration ................................................................................................. 241
11.4 Register Map .......................................................................................................................... 241
11.5 Register Descriptions .............................................................................................................. 242
12 Analog-to-Digital Converter (ADC) ................................................................................. 263
12.1 Block Diagram ........................................................................................................................ 264
12.2 Functional Description ............................................................................................................. 264
12.2.1 Sample Sequencers ................................................................................................................ 264
12.2.2 Module Control ........................................................................................................................ 265
12.2.3 Hardware Sample Averaging Circuit ......................................................................................... 266
12.2.4 Analog-to-Digital Converter ...................................................................................................... 266
12.2.5 Test Modes ............................................................................................................................. 266
12.2.6 Internal Temperature Sensor .................................................................................................... 266
12.3 Initialization and Configuration ................................................................................................. 267
12.3.1 Module Initialization ................................................................................................................. 267
12.3.2 Sample Sequencer Configuration ............................................................................................. 267
12.4 Register Map .......................................................................................................................... 268
12.5 Register Descriptions .............................................................................................................. 269
13 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 296
13.1 Block Diagram ........................................................................................................................ 297
13.2 Functional Description ............................................................................................................. 297
13.2.1 Transmit/Receive Logic ........................................................................................................... 297
13.2.2 Baud-Rate Generation ............................................................................................................. 298
13.2.3 Data Transmission .................................................................................................................. 299
13.2.4 Serial IR (SIR) ......................................................................................................................... 299
13.2.5 FIFO Operation ....................................................................................................................... 300
13.2.6 Interrupts ................................................................................................................................ 300
13.2.7 Loopback Operation ................................................................................................................ 301
13.2.8 IrDA SIR block ........................................................................................................................ 301
13.3 Initialization and Configuration ................................................................................................. 301
13.4 Register Map .......................................................................................................................... 302
November 30, 2007
5
Preliminary
Share Link: 