LM3S6965-IQN20A2T Просмотр технического описания (PDF) - Unspecified

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Компоненты Описание

производитель

LM3S6965-IQN20A2T

Microcontroller

Unspecified 

Table of Contents

6.1.3

6.1.4

6.1.5

6.2

6.3

6.4

7

7.1

7.2

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6

7.2.7

7.3

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.4

7.5

8

8.1

8.2

8.2.1

8.2.2

8.3

8.3.1

8.3.2

8.4

8.5

8.6

9

9.1

9.1.1

9.1.2

9.1.3

9.1.4

9.1.5

9.1.6

9.2

9.3

9.4

Power Control ........................................................................................................................... 62

Clock Control ............................................................................................................................ 62

System Control ......................................................................................................................... 64

Initialization and Configuration ................................................................................................... 65

Register Map ............................................................................................................................ 65

Register Descriptions ................................................................................................................ 66

Hibernation Module .......................................................................................................... 120

Block Diagram ........................................................................................................................ 121

Functional Description ............................................................................................................. 121

Register Access Timing ........................................................................................................... 121

Clock Source .......................................................................................................................... 122

Battery Management ............................................................................................................... 122

Real-Time Clock ...................................................................................................................... 122

Non-Volatile Memory ............................................................................................................... 123

Power Control ......................................................................................................................... 123

Interrupts and Status ............................................................................................................... 123

Initialization and Configuration ................................................................................................. 124

Initialization ............................................................................................................................. 124

RTC Match Functionality (No Hibernation) ................................................................................ 124

RTC Match/Wake-Up from Hibernation ..................................................................................... 124

External Wake-Up from Hibernation .......................................................................................... 125

RTC/External Wake-Up from Hibernation .................................................................................. 125

Register Map .......................................................................................................................... 125

Register Descriptions .............................................................................................................. 126

Internal Memory ............................................................................................................... 139

Block Diagram ........................................................................................................................ 139

Functional Description ............................................................................................................. 139

SRAM Memory ........................................................................................................................ 139

Flash Memory ......................................................................................................................... 140

Flash Memory Initialization and Configuration ........................................................................... 141

Flash Programming ................................................................................................................. 141

Nonvolatile Register Programming ........................................................................................... 142

Register Map .......................................................................................................................... 142

Flash Register Descriptions (Flash Control Offset) ..................................................................... 143

Flash Register Descriptions (System Control Offset) .................................................................. 150

General-Purpose Input/Outputs (GPIOs) ....................................................................... 163

Functional Description ............................................................................................................. 163

Data Control ........................................................................................................................... 164

Interrupt Control ...................................................................................................................... 165

Mode Control .......................................................................................................................... 166

Commit Control ....................................................................................................................... 166

Pad Control ............................................................................................................................. 166

Identification ........................................................................................................................... 166

Initialization and Configuration ................................................................................................. 166

Register Map .......................................................................................................................... 168

Register Descriptions .............................................................................................................. 169

4

November 30, 2007

Preliminary

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