LM3S6965-IQN20A2T Просмотр технического описания (PDF) - Unspecified

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LM3S6965-IQN20A2T

Microcontroller

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LM3S6965 Microcontroller

Table of Contents

About This Document .................................................................................................................... 20

Audience .............................................................................................................................................. 20

About This Manual ................................................................................................................................ 20

Related Documents ............................................................................................................................... 20

Documentation Conventions .................................................................................................................. 20

1

1.1

1.2

1.3

1.4

1.4.1

1.4.2

1.4.3

1.4.4

1.4.5

1.4.6

1.4.7

1.4.8

Architectural Overview ...................................................................................................... 22

Product Features ...................................................................................................................... 22

Target Applications .................................................................................................................... 28

High-Level Block Diagram ......................................................................................................... 29

Functional Overview .................................................................................................................. 30

ARM Cortex™-M3 ..................................................................................................................... 30

Motor Control Peripherals .......................................................................................................... 30

Analog Peripherals .................................................................................................................... 31

Serial Communications Peripherals ............................................................................................ 32

System Peripherals ................................................................................................................... 33

Memory Peripherals .................................................................................................................. 34

Additional Features ................................................................................................................... 35

Hardware Details ...................................................................................................................... 35

2

2.1

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

ARM Cortex-M3 Processor Core ...................................................................................... 37

Block Diagram .......................................................................................................................... 38

Functional Description ............................................................................................................... 38

Serial Wire and JTAG Debug ..................................................................................................... 38

Embedded Trace Macrocell (ETM) ............................................................................................. 39

Trace Port Interface Unit (TPIU) ................................................................................................. 39

ROM Table ............................................................................................................................... 39

Memory Protection Unit (MPU) ................................................................................................... 39

Nested Vectored Interrupt Controller (NVIC) ................................................................................ 39

3

Memory Map ....................................................................................................................... 43

4

Interrupts ............................................................................................................................ 45

5

5.1

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.3

5.4

5.4.1

5.4.2

JTAG Interface .................................................................................................................... 48

Block Diagram .......................................................................................................................... 49

Functional Description ............................................................................................................... 49

JTAG Interface Pins .................................................................................................................. 50

JTAG TAP Controller ................................................................................................................. 51

Shift Registers .......................................................................................................................... 52

Operational Considerations ........................................................................................................ 52

Initialization and Configuration ................................................................................................... 55

Register Descriptions ................................................................................................................ 55

Instruction Register (IR) ............................................................................................................. 55

Data Registers .......................................................................................................................... 57

6

6.1

6.1.1

6.1.2

System Control ................................................................................................................... 59

Functional Description ............................................................................................................... 59

Device Identification .................................................................................................................. 59

Reset Control ............................................................................................................................ 59

November 30, 2007

3

Preliminary

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