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LH5116SN

CMOS 16K (2K × 8) Static RAM

Sharp Electronics 

LH5116S

CMOS 16K (2K × 8) Static RAM

A0 - A10

tWC

tAW

tWR (NOTE 3)

tCW

CE

tAS

tWP

(NOTE 2)

WE

(NOTE 4)

tWHZ

tOW

(NOTE 5)

DOUT

tDW

tDH

(NOTE 6)

DIN

NOTES:

OE = 'LOW'

1. WE must be HIGH when there is a change in A0 - A10.

2. When CE and WE are both LOW at the same time, write occurs during the period tWP.

3. tWR is the time from the rise of CE or WE, whichever is first, to the end of the write cycle.

4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance.

5. DOUT outputs data with the same logic level as the input data of this write cycle.

6. If CE is LOW during this period, the input/output pins are in the output state. During this state, input

signals of opposite logic level must not be applied.

Figure 5. Write Cycle 1 (Note 1)

5116S-4

tWC

A0 - A10

OE

tAW

tCW

tWR

(NOTE 3)

CE

tAS

tWP

(NOTE 2)

WE

tOHZ

tOLZ

tOW

(NOTE 5)

DOUT

(NOTE 4)

tDW

tDH

(NOTE 6)

DIN

NOTES:

1. WE must be HIGH when there is a change in A0 - A10.

2. When CE and WE are both LOW at the same time, write occurs during the period tWP.

3. tWR is the time from the rise of CE or WE, whichever is first, to the end of the write cycle.

4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance.

5. DOUT outputs data with the same logic level as the input data of this write cycle.

6. If CE and OE are LOW during this period, the input/output pins are in the output state. During this state, input

signals of opposite logic level must not be applied.

Figure 6. Write Cycle 2 (Note 1)

5116S-5

6

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