LD39150DT12-R Просмотр технического описания (PDF) - STMicroelectronics

Номер в каталоге

Компоненты Описание

Список матч

LD39150DT12-R

Ultra low drop BICMOS voltage regulator

STMicroelectronics 

Pin configuration

2

Pin configuration

Figure 2. Pin connections (top view for DPAK and PPAK, bottom view for DFN)

LD39150

DFN8 (4x4 mm)

PPAK

DPAK

Table 1. Pin description

PlN N°

DFN PPAK DPAK

SYMBOL

NOTE

8

5

3, 4

2

6, 7

4

2

1

VSENSE/N.C.

For fixed versions: to be connected with LDO Output Voltage pins for DFN

package and Not Connected on PPAK

ADJ

For adjustable version: Error Amplifier Input pin for VO from 1.22 to 5.0V

1

VI

LDO Input Voltage; VI from 2.5V to 6V, CI=1µF must be located at a

distance of not more than 0.5’’ from input pin.

3

VO

LDO Output Voltage pins, with minimum CO=2.2µF needed for stability

(also refer to CO vs. ESR stability chart)

VINH

Inhibit Input Voltage: ON MODE when VINH ≥ 2V, OFF MODE when VINH ≤

0.3V (Do not leave floating, not internally pulled down/up)

1

3

2

5

GND

N.C.

Common ground

Not Connected

4/19

Share Link: