LD39150PT-R(2017) Просмотр технического описания (PDF) - STMicroelectronics

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LD39150PT-R
(Rev.:2017)

Ultra low drop BiCMOS voltage regulator

STMicroelectronics 

Pin configuration

2

Pin configuration

LD39150

Figure 2. Pin connections (top view for DPAK and PPAK, bottom view for DFN)

6

1

5

TAB

2

4

3

CS26660

DFN6 (3 x 3 mm)

TAB

PPAK

5

4

3

2

1

CS24140

TAB

3

2

1

CS24160

DPAK

Table 2. Pin description

Pin n°

DFN PPAK DPAK

SYMBOL

NOTE

5

5

VSENSE/N.C.

For fixed versions: to be connected with LDO output voltage pins for DFN

package and not connected on PPAK

ADJ

For adjustable version: Error amplifier input pin for VO from 1.22 to 5.0 V

3

2

1

VI

LDO input voltage; VI from 2.5 V to 6 V, CI = 1 µF must be located at a

distance of not more than 0.5’’ from input pin.

4

4

3

2

1

VO

VINH

LDO output voltage pins, with minimum CO = 2.2 µF needed for stability

(also refer to CO vs ESR stability chart)

Inhibit input voltage: ON MODE when VINH  2 V, OFF MODE when VINH 

0.3 V (Do not leave floating, not internally pulled down/up)

1

3

2

GND Common ground

6

N.C.

Not connected

TAB TAB

GND Electrically connected to GND

Exp.

Pad

Connect to GND (it is not a power GND)

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DocID13159 Rev 5

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