LC78836 Просмотр технического описания (PDF) - SANYO -> Panasonic

Номер в каталоге

Компоненты Описание

Список матч

LC78836

Digital Audio 16-Bit D/A Converter with On-Chip Digital Filters

SANYO -> Panasonic 

LC78836M

• Soft muting

Soft muting is implemented using the on-chip digital attenuator.

The attenuator attenuation is given by the following formula.

20 Log (ATT/64) dB

Here, ATT is an integer between 0 and 64 inclusive. However, the attenuation is –∞ when ATT = 0. When the

MUTE pin is set high, the ATT value is reduced one level at a time towards zero, and the attenuation changes,

moving towards –∞. When the MUTE pin is set low, the ATT value is increased one level at a time towards 64,

and the attenuation changes, moving towards 0 dB. The time required for the soft mute function to complete is

about 1024/fs.

• Noise shaper

The LC78836M uses a first-order noise shaper to reduce re-quantization noise in the output of the DF calculations.

• Double-speed support

The LC78836M supports double-speed CD playback when the D/N pin is set high. In this mode, the BCLK,

LRCK, and DATA inputs should be input with twice the frequencies they have in standard-speed mode. Note that

the system clock (the XIN pin clock) has the same frequency as it does in standard-speed mode. The LC78836M

supports double-speed operation when the system clock is a 384 fs or 512 fs clock, but does not support this mode

for 392 fs and 448 fs clocks. Since the LC78836M enters test mode for these settings, they should not be used.

Standard-speed mode: D/N pin = low

Double-speed mode: D/N pin = high

2. Initialization

The LC78836M must be initialized when power is first applied or when the system clock is switched. Initialization is

executed by setting the INITB pin low. While that pin is low, after the power supply voltage stabilizes, input the

XIN, BCLK, and LRCK signals, and wait at least one LRCK period, as shown in the figure below.

When INITB is low, all 16 bits of the digital filter outputs will be zeros, and the D/A converter outputs (CH1OUT

and CH2OUT) will be analog 0 (a potential essentially equal to (VREFH + VREFL)/2).

No. 5127-6/12

Share Link: