LC3564CT Просмотр технического описания (PDF) - SANYO -> Panasonic

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LC3564CT

64K (8192-word × 8-bit) SRAM with OE, CE1, and CE2 Control Pins

SANYO -> Panasonic 

Write Cycle (2): CE1 Write *6

A0 to A12

tAS

WE

LC3564CM, CT-55U/70U

tWC

tWP *3

tWR1

CE2

CE1

*5

DOUT1 to 8

tCOE1

DIN1 to 8

INVALID DATA

Write Cycle (3): CE2 Write *6

A0 to A12

tAS

WE

tCW2 *4

tCW1 *4

tWOD

tDS

tDH1

DATA IN STABLE

H or L

tWC

tWP *3

tWR2

A13515

CE2

CE1

*5

DOUT1 to 8

DIN1 to 8

tCOE2

tCW2 *4

tCW1 *4

tWOD

tDS

tDH2

DATA IN STABLE

INVALID DATA

H or L

A13516

Notes: 1. Hold WE high during the read cycle.

2. Applications must not apply reverse phase signals to the DOUT pins when those pins are in the output state.

3. The time tWP is the period when CE1 and WE are low and CE2 is high, and is defined as the time from the fall of WE until either CE1 or WE rises,

or CE2 falls, whichever occurs first.

4. The times tCW1 and tCW2 are periods when CE1 and WE are low and CE2 is high. They are defined as the times from the fall of CE1 or the rise of

CE2 to the rise of CE1 and WE, or the fall of CE2, whichever occurs first.

5. The DOUT pins will be in the high-impedance state if either OE is high, CE1 is high, CE2 is low, or WE is low.

6. OE must be held either at VIH or VIL during the write cycle.

7. The DOUT pins have the same phase as the write cycle write data.

No. 6635-9/11

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