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LUCL9313AP

Line Interface and Line Access Circuit Full-Feature SLIC and Ringing Relay for TR-57 Applications

Agere -> LSI Corporation 

Data Sheet

September 2001

L9313 Line Interface and Line Access Circuit

Full-Feature SLIC and Ringing Relay for TR-57 Applications

Description (continued)

The L9313 uses a voltage feed, current sense architec-

ture; thus, the transmit gain is a transconductance. The

L9313 transconductance is set via a single external

resistor, and this device is designed for optimal perfor-

mance with a transconductance set at 300 V/A.

The L9313 offers an option for a single-ended to differ-

ential receive gain of either 8 or 2. These options are

mask programmable at the factory and are selected by

choice of part number.

A receive gain of 8 is more appropriate when choosing

a first-generation type codec where termination imped-

ance, hybrid balance, and overall gains are set by

external analog filters. The higher gain is typically

required for synthesization of complex termination

impedance.

A receive gain of 2 is more appropriate when choosing

a third-generation type codec. Third-generation codecs

will synthesize termination impedance, set hybrid bal-

ance, and set overall gains. To accomplish these func-

tions, third-generation codecs typically have both

analog and digital gain filters. For optimal signal-to-

noise performance, it is best to operate the codec at a

higher gain level. If the SLIC then provides a high gain,

the SLIC output may be saturated causing clipping dis-

tortion of the signal at tip and ring. To avoid this situa-

tion, with a higher-gain SLIC, external resistor dividers

are used. These external components are not neces-

sary with the lower gain offered by the L9313.

The RCVP/RCVN SLIC inputs are floating inputs. If

there is not feedback from RCVP/RCVN to VITR,

RCVP/RCVN may be directly coupled to the codec out-

put. If there is feedback, RCVP/RCVN must be ac-cou-

pled to the codec output.

This device is packaged in a 44-pin PLCC surface-

mount package.

Architecture

VITR

LCF

LCTH RESET NSTAT LATCH B2 B1 B0 VPROG VDD DGND

VREF

TXI

–

AAC

+

VTX

(1 V/50 mA)

ITR

+

AX

–

SWITCHHOOK

WINDOW

COMPARATOR

IN REF

PARALLEL DATA INTERFACE

RT CONTROL

FB

ILC

RB

VTX

2.35 V

BANDGAP

REFERENCE

2.35 V

VREF

CURRENT LIMITER

AND

INRUSH CONTROL

IN

REF

CF2

CF2

+5VD

TRNG

PT

PR

RTS

RSW

RRING

SW3

60 Ω

SW1

18 Ω

VITR

SW2

18 Ω

BGND ITR/325

RFT

VBAT ITR

BGND

TIP/RING

CURRENT

SENSE

ITR

RFR

ILC

SCAN

&

RING GND

DETECTOR

VBAT

RING TRIP RT

DETECTOR

SW4

15 Ω

+5VA

SCAN

VBAT

BGND

SCAN

CLAMP

BGND

+

OUT AT

–

VBAT

ac

ac

INTERFACE

BGND

+

OUT AR

–

VBAT

x1

dc

x1

VBAT

FBRB

FB

VCC AGND

RGDET ICM VBAT2/PWR

VBAT1 VBAT1 BGND BGND

Figure 1. Architecture Diagram

RCVP

RCVN

FB1

CF1

OVH

CF2

FB2

Agere Systems Inc.

12-3523f (F)

7

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