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LUCL9313AP

Line Interface and Line Access Circuit Full-Feature SLIC and Ringing Relay for TR-57 Applications

Agere -> LSI Corporation 

L9313 Line Interface and Line Access Circuit

Full-Feature SLIC and Ringing Relay for TR-57 Applications

Data Sheet

September 2001

Pin Information (continued)

Table 1. Pin Descriptions (continued)

Pin Symbol Type

Name/Function

35 ICM

I Common-Mode Current Sense. To program tip or ring ground sense threshold, connect

a resistor to ground and connect a capacitor to AGND to filter 50 Hz/60 Hz. If unused, the

pin is connected to ground.

36 VTX

O Tip/Ring Voltage Output. This output is a voltage that is directly proportional to the differ-

ential tip/ring current. A resistor from this node to ITR sets the device transimpedance.

Gain shaping for termination impedance with a COMBO I codec is also achieved with a

network from this node to ITR.

37 ITR

I Transmit Gain. A current output which is proportional to the differential current flowing

from tip to ring. Input to AX amplifier. Connect a resistor from this node to VITR to set

transmit gain to 300 Ω. Gain shaping for termination impedance with a COMBO I codec is

also achieved with a network from this node to VITR.

39 TXI

I Transmit ac Input (Noninverting). Connect a 0.1 µF capacitor from this pin to VTX for dc

blocking.

40 VITR

O Transmit ac Output Voltage. The output is a voltage that is directly proportional to the dif-

ferential ac tip/ring current. This output is connected via a proper interface network to the

codec.

41 RCVP

I Receive ac Signal Input (Noninverting). This high-impedance input controls the ac dif-

ferential voltage on tip and ring.

42 RCVN I Receive ac Signal Input (Inverting). This high-impedance input controls the ac differen-

tial voltage on tip and ring.

43 AGND G Analog Ground. Ground return for VCC current.

44 VCC

P 5 V Analog Power Supply. 5 V supply for analog circuitry.

Operating States

Input State Coding

Data control is via a parallel latched data control scheme. Data latches are edge-level sensitive. Data is latched in

when the LATCH control input goes low. Data must be set up 200 ns before LATCH goes low and held 50 ns after

LATCH goes high. While LATCH is low, the user should not change the data control inputs at B0, B1, and B2. The

data control inputs at B0, B1, and B2 may only be changed when LATCH is high. NSTAT supervision output is not

controlled by the LATCH control input.

Table 2. Control States

B2

B1

B0

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

X

X

X

RESET

1

1

1

1

1

1

1

1

0

State

Scan

Powerup, forward battery

Powerup, reverse battery

Unassigned

Ring

Tip amp

Ring amp

Disconnect, break before make

Disconnect, break before make

10

Agere Systems Inc.

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