KSZ8842-MQL Просмотр технического описания (PDF) - Micrel

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KSZ8842-MQL

2-Port Ethernet Switch with Non-PCI Interface

Micrel 

Micrel, Inc.

Ball Number Ball Name

C3

SWR

A2

AEN

B2

WRN

A1

ADSN

B1

PWRDN

C1

RXP1

C2

RXM1

D1

TXP1

D2

TXM1

F2

RXM2

F1

RXP2

G2

TXM2

G1

TXP2

H2

TEST2

G3

ISET

J1

X1

K1

X2

J2

RSTN

K2

A15

K3

A14

J3

A13

H3

A12

K4

A11

J4

A10

H4

A9

K5

A8

J5

A7

H5

A6

K6

A5

J6

A4

H6

A3

K7

A2

October 2007

Type

Ipd

Ipu

Ipd

Ipd

Ipu

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Ipu

O

I

O

Ipu

I

I

I

I

I

I

I

I

I

I

I

I

I

I

KSZ8842-16/32 MQL/MVL/MVLI/MBL

Ball Function

This ball can be pull-down for 8-bit bus mode, pull-up for 16-bit bus mode or

don’t care for 32-bit bus mode when EEEN is pull-down (without EEPROM).

Synchronous Write/Read

Write/Read signal for synchronous bus accesses. Write cycles when high and

Read cycles when low.

Address Enable

Address qualifier for the address decoding, active Low.

Write Strobe Not

Asynchronous write strobe, active Low.

Address Strobe Not

For systems that require address latching, the rising edge of ADSN indicates the

latching moment of A15-A1 and AEN.

Full-chip power-down. Low = Power down; High or floating = Normal operation.

Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential)

Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential)

Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential)

Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential)

Port 2 physical receive (MDI) or transmit (MDIX) signal (- differential)

Port 2 physical receive (MDI)or transmit (MDIX) signal (+ differential)

Port 2 physical transmit (MDI) or receive (MDIX) signal (- differential)

Port 2 physical transmit (MDI) or receive (MDIX) signal (+ differential)

Test input 2

For normal operation, left this ball open.

Set physical transmits output current.

Pull-down this ball with a 3.01K 1% resistor to ground.

25MHz crystal or oscillator clock connection.

Balls (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V

tolerant oscillator and X2 is a no connect.

Note: Clock requirement is ± 50ppm for either crystal or oscillator.

Hardware reset ball (active Low). This reset input is required minimum of 10ms

low after stable supply voltage 3.3V.

Address 15

Address 14

Address 13

Address 12

Address 11

Address 10

Address 9

Address 8

Address 7

Address 6

Address 5

Address 4

Address 3

Address 2

20

M9999-102207-1.9

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