KSZ8841-PMQL(2006) Просмотр технического описания (PDF) - Micrel

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KSZ8841-PMQL
(Rev.:2006)

Single-Port Ethernet MAC Controller with PCI Interface

Micrel 

Micrel, Inc.

KSZ8841-PMQL

Physical Layer Transceiver (PHY)

100BASE-TX Transmit

The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI

conversion, and MLT3 encoding and transmission.

The circuitry starts with a parallel-to-serial conversion, which converts the 25MHz 4-bit nibbles into a 125MHz serial bit

stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data

is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. An external 1% 3.01KΩ

resistor for the 1:1 transformer ratio sets the output current.

The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude

balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output driver is also incorporated into the 100BASE-

TX driver.

100BASE-TX Receive

The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data

and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.

The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted

pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its

characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on

comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for

optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature

variations.

Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used

to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion

circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.

The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then

used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B

decoder. Finally, the NRZ serial data is converted to an MII format and provided as the input data to the MAC.

PLL Clock Synthesizer (Recovery)

The internal PLL clock synthesizer generates 125MHz, 62.5MHz, 41.66MHz, and 25MHz clocks by setting the on-chip

bus speed control register OBCR for KSZ8841-PMQL system timing. These internal clocks are generated from an

external 25MHz crystal or oscillator.

Note: Default setting is 25MHz in OBCR register, recommends the software driver to set it to 125MHz for best

performance.

Scrambler/De-scrambler (100BASE-TX Only)

The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference

(EMI) and baseline wander.

Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler

generates a 2047-bit non-repetitive sequence. Then the receiver de-scrambles the incoming data stream using the

same sequence as at the transmitter.

10BASE-T Transmit

The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetic.

They are internally wave-shaped and pre-emphasized into outputs with typical 2.4V amplitude. The harmonic contents

are at least 27dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.

10BASE-T Receive

On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit

and a phase-locked loop (PLL) perform the decoding function.

The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals

with levels less than 400mV or with short pulse widths to prevent noise at the RXP-or-RXM input from falsely triggering

June 2006

16

M9999-061206-1.2

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