K6X1008C2D Просмотр технического описания (PDF) - Samsung

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K6X1008C2D

128K x 8 bit Low Power CMOS Static RAM

Samsung 

K6X1008C2D Family

CMOS SRAM

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)

Address

Data Out

tRC

tAA

tOH

Previous Data Valid

Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Address

CS1

tRC

tAA

tCO1

CS2

OE

Data out

High-Z

tCO2

tOE

tOLZ

tLZ

tOH

tHZ(1,2)

Data Valid

tOHZ

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

6

Revision 1.0

September 2003

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