YMF715E Просмотр технического описания (PDF) - Yamaha Corporation

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YMF715E

5.0/3.3V; OPL3-SA3 OPL3 single-chip audio system 3

Yamaha Corporation 

YMF715E

BLOCK DIAGRAM

Tim. Generator

ISA BUS

Interface

VREF

Capture

A/D

FIFO

Data

Format

A/D

RESET

Plug

and

Play

D[7-0] 8

A[11-0] 12

AEN

/IOW

/IOR

Configuration

Register

I/O address

DMA channel

IRQ channel

Loop

Attn.

Play

D/A

FIFO

Data

Format

D/A

3

/DACK[0,1,3]

DRQ[0,1,3] 3

IRQ[11,10,9 6

7,5,3]

Decode

Logic

OPL3

FM Synthesizer

ML/I2S

S/P

16step

16step

Input Gain

64step

64step

+20dB

MIC

MONO_LOOP

AUX1R

AUX1L

LINER

LINEL

LOOP

AUX1

32step

LINE

32step

32step MIC

3D

Enhanced

Control

16step

Master

16step

64step

VOCOL

VOCOR

VOCIR

VOCIL

OUTL

OUTR

2

2

/VOLUP,

/VOLDW

TRECL/R

MIN

32step AUX2

AUX2L

AUX2R

Synth.

D/A

8step

SB

D/A

2 SBFLTL/R

Control

Register

MUX

512 byte

SRAM

Multi-purpose

MUltipleX

i) 16bit Decode ii) EEPROM I/F

iii) ZV Port

iv) OPL4-ML I/F

v) MODEM I/F vi) CDROM I/F

3 10

Joy Stick

Logic

Port

MPU401

UART

with FIFO

44 2

SB Pro Mixer Register

Sound Blaster Pro

Command Interpreter

May 21, 1998

-5-

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