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YMF724 Просмотр технического описания (PDF) - Yamaha Corporation

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Компоненты Описание
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YMF724 Datasheet PDF : 50 Pages
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YMF724F
00 - 01h: Vendor ID
Read Only
Default: 1073h
Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Vendor ID
b[15:0] ........Vendor ID
This register contains the YAMAHA Vendor ID registered in Revision 2.1. This register is hardwired to
1073h.
02 - 03h: Device ID
Read Only
Default: 000Dh
Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Device ID
b[15:0] ........Device ID
This register contains the Device ID of DS-1. This register is hardwired to 000Dh.
04 - 05h: Command
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
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- SER - PER -
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- BME MS
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b1................MS: Memory Space
This bit enables DS-1 to response to Memory Space Access.
“0”: DS-1 ignores Memory Space Access.
(default)
“1”: DS-1 responds to Memory Space Access.
b2................BME: Bus Master Enable
This bit enables DS-1 to act as a master device on the PCI bus.
“0”: Do not set DS-1 to be the master device.
(default)
“1”: Set DS-1 to be the master device.
b6................PER: Parity Error Response
This bit enables DS-1 responses to Parity Error.
“0”: DS-1 ignores all parity errors.
“1”: DS-1 performs error operation when DS-1 detects a parity error.
January 14, 1999
-11-

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