ISPLSI2032A-180LJI Просмотр технического описания (PDF) - Lattice Semiconductor

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ISPLSI2032A-180LJI

In-System Programmable High Density PLD

Lattice Semiconductor 

Specifications ispLSI 2032/A

External Timing Parameters

Over Recommended Operating Conditions

PARAMETER

TEST 4

COND.

#2

DESCRIPTION1

-110

-80

UNITS

MIN. MAX. MIN. MAX.

tpd1

A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass

– 10.0 – 15.0 ns

tpd2

fmax

fmax (Ext.)

fmax (Tog.)

tsu1

tco1

th1

tsu2

tco2

A 2 Data Propagation Delay

A

3 Clock Frequency with Internal Feedback 3

–

4

Clock

Frequency

with

External

Feedback

(

1

tsu2 +

) tco1

– 5 Clock Frequency, Max. Toggle

– 6 GLB Reg. Setup Time before Clock, 4 PT Bypass

A 7 GLB Reg. Clock to Output Delay, ORP Bypass

– 8 GLB Reg. Hold Time after Clock, 4 PT Bypass

– 9 GLB Reg. Setup Time before Clock

– 10 GLB Reg. Clock to Output Delay

– 13.0 – 18.5

111 – 84.0 –

S 77.0 – 57.0 –

N 125 – 83.0 –

IG 5.5 – 7.5 –

– 5.5 – 8.0

S 0.0 – 0.0 –

E 7.5 – 9.5 –

D– 6.5 – 9.5

ns

MHz

MHz

MHz

ns

ns

ns

ns

ns

th2

tr1

trw1

tptoeen

– 11 GLB Reg. Hold Time after Clock

A 12 Ext. Reset Pin to Output Delay

– 13 Ext. Reset Pulse Duration

B 14 Input to Output Enable

0.0

W–

E 6.5

N–

– 0.0 –

13.5 – 19.5

– 10.0 –

14.5 – 24.0

ns

ns

ns

ns

tptoedis

tgoeen

tgoedis

twh

C

B

C

–

15

16

17

18

Input to Output Disable

R Global OE Output Enable

Global OE Output Disable

FO External Synchronous Clock Pulse Duration, High

– 14.5 – 24.0 ns

– 7.0 – 12.0 ns

– 7.0 – 12.0 ns

4.0 – 6.0 –

ns

twl

– 19 External Synchronous Clock Pulse Duration, Low

4.0

E 1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.

2 2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.

ispLSI 203 4. Reference Switching Test Conditions section.

–

6.0 –

ns

Table 2-0030B-110/2032

USE

6

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