ISPLSI2032A-135LJ44 Просмотр технического описания (PDF) - Lattice Semiconductor

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ISPLSI2032A-135LJ44

In-System Programmable High Density PLD

Lattice Semiconductor 

Specifications ispLSI 2032/A

Functional Block Diagram

Figure 1. ispLSI 2032/A Functional Block Diagram

GOE 0

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

A0

A1

A2

Global Routing Pool

(GRP)

A7

IGNS I/O 31

SI/O 30

I/O 29

I/O 28

E I/O 27

D I/O 26

A6

NEWA5

I/O 25

I/O 24

I/O 23

I/O 22

I/O 21

I/O 20

I/O 19

I/O 13

I/O 14

A3

I/O 15

SDI/IN 0

SDO/IN 1

FOR

A4

I/O 18

I/O 17

I/O 16

MODE

ispEN

2E Notes:

3 *Y1 and RESET are multiplexed on the same pin

I 20 The devices also have 32 I/O cells, each of which is

S directly connected to an I/O pin. Each I/O cell can be

individually programmed to be a combinatorial input,

L output or bi-directional I/O pin with 3-state control. The

p signal levels are TTL compatible voltages and the output

is drivers can source 4 mA or sink 8 mA. Each output can

Y0

*Y1/RESET

SCLK/Y2

0139B(1)isp/2000

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

Clocks in the ispLSI 2032 and 2032A devices are se-

lected using the dedicated clock pins. Three dedicated

clock pins (Y0, Y1, Y2) or an asynchronous clock can be

be programmed independently for fast or slow output

slew rate to minimize overall output switching noise.

SE Eight GLBs, 32 I/O cells, two dedicated inputs and two

U ORPs are connected together to make a Megablock

selected on a GLB basis. The asynchronous or Product

Term clock can be generated in any GLB for its own clock.

(Figure 1). The outputs of the eight GLBs are connected

to a set of 32 universal I/O cells by the ORP. Each ispLSI

2032 and 2032A device contains one Megablock.

The GRP has as its inputs, the outputs from all of the

GLBs and all of the inputs from the bi-directional I/O cells.

All of these signals are made available to the inputs of the

2

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