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ISP1582

Hi-Speed Universal Serial Bus peripheral controller

Philips Electronics 

Philips Semiconductors

ISP1582

Hi-Speed USB peripheral controller

8. Functional description

The ISP1582 is a high-speed USB peripheral controller. It implements the Hi-Speed

USB or the Original USB physical layer and the packet protocol layer. It maintains up

to 16 USB endpoints concurrently (control IN and control OUT, 7 IN and 7 OUT

configurable) along with endpoint EP0 setup, which accesses the setup buffer. The

USB Chapter 9 protocol handling is executed by means of external firmware.

For high-bandwidth data transfer, the integrated DMA handler can be invoked to

transfer data to or from external memory or devices. The DMA interface can be

configured by writing to the proper DMA registers (see Section 9.4).

The ISP1582 supports Hi-Speed USB and Original USB signaling. The USB

signaling speed is automatically detected.

The ISP1582 has 8 kbytes of internal FIFO memory, which is shared among the

enabled USB endpoints.

There are 7 IN endpoints, 7 OUT endpoints and 2 control endpoints that are a fixed

64 bytes long. Any of the 7 IN and 7 OUT endpoints can be separately enabled or

disabled. The endpoint type (interrupt, isochronous or bulk) and packet size of these

endpoints can be individually configured depending on the requirements of the

application. Optional double buffering increases the data throughput of these data

endpoints.

The ISP1582 requires 3.3 V power supply. It has 5 V tolerant I/O pads when

operating at VCC(I/O) = 3.3 V and an internal 1.8 V regulator for powering the analog

transceiver.

The ISP1582 operates on a 12 MHz crystal oscillator. An integrated 40 × PLL clock

multiplier generates the internal sampling clock of 480 MHz.

8.1 DMA interface, DMA handler and DMA registers

The DMA block can be subdivided into two blocks: the DMA handler and the DMA

interface.

The firmware writes to the DMA command register to start a DMA transfer (see

Table 47). The command opcode determines whether a generic DMA or PIO transfer

will start. The handler interfaces to the same FIFO (internal RAM) as used by the

USB core. On receiving the DMA command, the DMA handler directs the data from

the endpoint FIFO to the external DMA device or from the external DMA device to the

endpoint FIFO.

The DMA interface configures the timing and the DMA handshake. Data can be

transferred using either the DIOR and DIOW strobes or by the DACK and DREQ

handshakes. The DMA configurations are set up by writing to the DMA Configuration

register (see Table 52 and Table 53).

For a generic DMA interface, Generic DMA (GDMA) slave mode can be used.

Remark: The DMA endpoint buffer length must be a multiple of 4 bytes.

For details on DMA registers, see Section 9.4.

9397 750 13699

Preliminary data

Rev. 03 — 25 August 2004

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

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