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ISP1562BE

Hi-Speed Universal Serial Bus PCI Host Controller

Philips Electronics 

Philips Semiconductors

ISP1562

USB PCI Host Controller

Table 17: BAR 0 - Base Address register 0 (address 10h) bit description

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 0 BAR 0[31:0] R/W

0000 Base Address to Memory-Mapped Host Controller

0000h* Register Space: The memory size required by OHCI

and EHCI are 4 kB and 256 B, respectively. Therefore,

BAR 0[31:12] is assigned to the two OHCI ports, and

BAR 0[31:8] is assigned to the EHCI port.

8.2.1.11 Subsystem Vendor ID register

The Subsystem Vendor ID register is used to uniquely identify the expansion board or

subsystem where the PCI device resides. This register allows expansion board vendors to

distinguish their boards, even though the boards may have the same Vendor ID and

Device ID.

Subsystem Vendor IDs are assigned by PCI-SIG to maintain uniqueness. The bit

description of the Subsystem Vendor ID register is given in Table 18.

Table 18: SVID - Subsystem Vendor ID register (address 2Ch) bit description

Legend: * reset value

Bit

Symbol Access Value Description

15 to 0 SVID[15:0] R

1131h* Subsystem Vendor ID: 1131h is the subsystem

Vendor ID assigned to Philips Semiconductors.

8.2.1.12 Subsystem ID register

Subsystem ID values are vendor specific. The bit description of the Subsystem ID register

is given in Table 19.

Table 19: SID - Subsystem ID register (address 2Eh) bit description

Legend: * reset value

Bit

Symbol

Access Value Description

15 to 0 SID[15:0] R

156Xh* [1] Subsystem ID: For the ISP1562, Philips

Semiconductors has defined OHCI functions as

1561h, and the EHCI function as 1562h.

[1] X is 1h for OHCI1 and OHCI2; X is 2h for EHCI.

8.2.1.13 Capabilities Pointer register

This register is used to point to a linked list of new capabilities implemented by the device.

This register is only valid if CL (bit 4 in the Status register) is set. If implemented, bit 1 and

bit 0 are reserved and should be set to 00b. Software should mask these bits off before

using this register as a pointer in configuration space to the first entry of a linked list of

new capabilities. The bit description of the register is given in Table 20.

Table 20: CP - Capabilities Pointer register (address 34h) bit description

Legend: * reset value

Bit Symbol Access Value Description

7 to 0 CP[7:0] R

DCh*

Capabilities Pointer: EHCI efficiently manages power

using this register. This Power Management register is

allocated at offset DCh. Only one Host Controller is

needed to manage power in the ISP1562.

9397 750 14223

Product data sheet

Rev. 01 — 14 July 2005

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

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