ISP1183 Просмотр технического описания (PDF) - Philips Electronics
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ISP1183 Datasheet PDF : 62 Pages
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Philips Semiconductors
ISP1183
Low-power USB interface device with DMA
XTAL2
6
ISP1183
XTAL1
7
18 pF
6 MHz
18 pF
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Fig 5. Typical oscillator circuit.
The 6 MHz oscillator frequency is multiplied to 48 MHz by an internal PLL.
In the suspend state, the crystal oscillator and the PLL are switched off to save
power. The oscillator operation is controlled by using bit CLKRUN in the Hardware
Configuration register. CLKRUN switches the oscillator on and off.
8.13 Power-on reset
The ISP1183 has an internal power-on reset (POR) circuit. The clock signal normally
requires 3 ms to 4 ms to stabilize.
The triggering voltage of the POR circuit is 0.5 V nominal. A POR is automatically
generated when VDD(I/O) goes below the trigger voltage for a duration longer than
50 µs.
VDD(I/O)
0.5 V
POR
≤ 350 µs
2 ms
0V
t1
t1: clock is running
t2: registers are accessible
Fig 6. POR timing.
t2
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9397 750 11804
Product data
POR
EXTERNAL CLOCK
A
Stable external clock available at A.
Fig 7. Clock with respect to the external POR.
Rev. 01 — 24 February 2004
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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