ISP1161A Просмотр технического описания (PDF) - Philips Electronics
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ISP1161A Datasheet PDF : 134 Pages
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Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Figure 9 shows the DMA interface between a microprocessor system and the
ISP1161A. The ISP1161A provides two DMA channels:
• DMA channel 1 (controlled by DREQ1, DACK1 signals) is for the DMA transfer
between a microprocessor’s system memory and ISP1161A HC internal FIFO
buffer RAM
• DMA channel 2 (controlled by DREQ2, DACK2 signals) is for the DMA transfer
between a microprocessor system memory and the ISP1161A DC internal FIFO
buffer RAM.
The EOT signal is an external end-of-transfer signal used to terminate the DMA
transfer. Some microprocessors may not have this signal. In this case, the ISP1161A
provides an internal EOT signal to terminate the DMA transfer as well. Setting the
HcDMAConfiguration register (21H - read, A1H - write) enables the ISP1161A HC
internal DMA counter for DMA transfer. When the DMA counter reaches the value set
in the HcTransferCounter register (22H - read, A2H - write), an internal EOT signal
will be generated to terminate the DMA transfer.
9397 750 13962
Product data
D [15:0]
µP bus I/F
D [15:0]
RD
RD
WR
WR
MICRO-
DACK1
PROCESSOR DREQ1
DACK1 ISP1161A
DREQ1
DACK2
DREQ2
DACK2
DREQ2
EOT
EOT
004aaa087
Fig 9. DMA interface between a microprocessor and an ISP1161A.
8.3 Control register access by PIO mode
8.3.1 I/O port addressing
Table 3 shows the ISP1161A I/O port addressing. Complete decoding of the I/O port
address should include the chip select signal CS and the address lines A1 and A0.
However, the direction of the access of the I/O ports is controlled by the RD and WR
signals. When RD is LOW, the microprocessor reads data from the ISP1161A data
port. When WR is LOW, the microprocessor writes a command to the command port,
or writes data to the data port.
Table 3: I/O port addressing
Port Pin CS Pin A1 Pin A0
0 LOW LOW
LOW
1 LOW LOW
HIGH
2 LOW HIGH
LOW
3
LOW HIGH
HIGH
Access
R/W
W
R/W
W
Data bus width Description
16 bits
HC data port
16 bits
HC command port
16 bits
DC data port
16 bits
DC command port
Rev. 03 — 23 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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