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ISL97671A

6-Channel SMBus/I2C or PWM Dimming LED Driver with Phase Shift Control

Intersil 

ISL97671A

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

PART

MARKING

PACKAGE

(Pb-free)

PKG.

DWG. #

ISL97671AIRZ

671A

20 Ld 3x4 QFN L20.3x4

ISL97671AIRZ-EVALZ Evaluation Board

NOTES:

1. Add “-T* suffix for tape and reel. Please refer to TB347 for details on

reel specifications.

2. These Intersil Pb-free plastic packaged products employ special

Pb-free material sets, molding compounds/die attach materials, and

100% matte tin plate plus anneal (e3 termination finish, which is

RoHS compliant and compatible with both SnPb and Pb-free

soldering operations). Intersil Pb-free products are MSL classified at

Pb-free peak reflow temperatures that meet or exceed the Pb-free

requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information

page for ISL97671A. For more information on MSL please see

techbrief TB363.

Pin Configuration

ISL97671A

(20 LD QFN)

TOP VIEW

FAULT 1

VIN 2

EN 3

VDC 4

PWM 5

SMBDAT/SDA 6

20 19 18 17

7 8 9 10

16 OVP

15 CH5

14 CH4

13 CH3

12 CH2

11 CH1

Pin Descriptions (I = Input, O = Output, S = Supply, X = Don’t Care)

PIN NAME

PIN # TYPE

DESCRIPTION

FAULT

1

O Fault Disconnect Switch Gate Control.

VIN

2

S Input voltage for the device and LED power.

EN

3

I The device needs 4ms for initial power-up enable. It will be disabled if it is not biased for longer than 28ms.

VDC

4

S De-couple capacitor for internally generated supply rail.

PWM

5

I PWM brightness control pin or DPST control input.

SMBDAT/SDA*

6

I/O SMBus/I2C serial data input and output. When pins 6 and 7 are grounded or in logic 0’s for longer than 60ms, the

drivers will be controlled by external PWM signal.

SMBCLK/SCL*

7

I SMBus/I2C serial clock input. When pins 6 and 7 are grounded or in logic 0’s for longer than 60ms, the drivers will

be controlled by external PWM signal.

FPWM

8

I Set PWM dimming frequency, FPWM by connecting a resistor. When FPWM ties to VDC and SMBCLK/SMBDAT tie

to ground, the device will be in Direct PWM Dimming where the output follows the input frequency and duty cycle

without any digitization.

AGND

9

S Analog Ground for precision circuits.

CH0, CH1

CH2, CH3

CH4, CH5

10, 11,

12, 13,

14, 15

I Input 0, Input 1, Input 2, Input 3, Input 4, Input 5 to current source, FB, and monitoring.

OVP

16

I Overvoltage protection input.

RSET

COMP

17

I Resistor connection for setting LED current, (see Equation 2 for calculating the ILED(peak)).

18

O Boost compensation pin.

PGND

19

S Power ground

LX

20

O Input to boost switch.

EPAD

No electrical connection but should be used to connect PGND and AGND. For example uses top plane as PGND and

bottom plane as AGND with vias on EPAD to allow heat dissipation and minimum noise coupling from PGND to

AGND operation.

3

FN7709.1

March 24, 2011

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