ISL97653AIRZ(2008) Просмотр технического описания (PDF) - Intersil

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ISL97653AIRZ
(Rev.:2008)

5-Channel Integrated LCD Supply

Intersil 

ISL97653A

Pin Descriptions (Continued)

PIN NUMBER

PIN NAME

25

CDEL

26

EN

27

HVS

28

RSET

29

FBB

30

COMP

31

TEMP

32, 33

34, 35

36

PGND1, 2

LX1, 2

PROT

37

AGND

38

PVIN1

39

LDO-FB

40

LDO-CTL

DESCRIPTION

VON slice control delay input. Minimum 47nF. Recommend 220nF but is only limited by leakage in the

cap reaching µA levels.

Chip enable (active high). Can be driven to VIN levels.

High-voltage stress input select pin. High selects high voltage mode.

Voltage set pin for HVS test. RSET connects to ground in the high voltage mode - RSET high.

AVDD boost feedback pin. High impedance input to regulate at 1.215V.

Boost compensation network pin. An RC network is recommended. Increase R for better transient

response at the expense of stability. An R = 0Ω is recommended for 4.4A Boost requirements.

Temperature sensor output voltage. An analog voltage from 0V to 3V for temperatures of -40°C to

+150°C.

Boost ground pins.

Boost switch output. Drain of the internal power NMOS for the Boost.

Gate driver of the Input protection switch. Goes low when EN is high. Can be used to modulate the

passive input inrush current as shown by R21,R22, and C30 in the typical application diagram.

Analog ground. Separate from PGND’s and star under the chip.

Logic buck supply voltage.This is also the analog supply from which the VL is generated. Needs at least

1µF bypassing.

LDO controller feedback. High impedance input to regulate at 1.215V.

LDO control pin. Gate drive for the external PNP BJT.

10

FN6367.1

February 21, 2008

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