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ISL84581 Просмотр технического описания (PDF) - Intersil

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ISL84581 Datasheet PDF : 15 Pages
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ISL84581
Test Circuits and Waveforms (Continued)
3V
LOGIC
INPUT
0V
VNO0
SWITCH
OUTPUT
0V
VNOX
50%
tTRANS
VOUT
tr < 20ns
tf < 20ns
90%
10%
C
V+
V-
C
LOGIC
INPUT
V+
C
V-
C
NO0
NO7
NO1-NO6
COM
ADDA-C GND INH
VOUT
RL
300Ω
CL
35pF
tTRANS
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for other switches. CL includes fixture and stray
capacitance.
VOUT
=
V(NO or NC)
---------R-----L---------
RL + rON
FIGURE 1C. ADDRESS tTRANS MEASUREMENT POINTS
FIGURE 1D. ADDRESS tTRANS TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
C
V-
C
LOGIC OFF
INPUT
ON
SWITCH
OUTPUT
VOUT
3V
OFF
0V
ΔVOUT
RG
NO
COM
VOUT
0Ω
ADDX
VG
GND INH
CL
LOGIC
1nF
INPUT
Q = ΔVOUT x CL
FIGURE 2A. Q MEASUREMENT POINTS
Repeat test for other switches.
FIGURE 2B. Q TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
3V
LOGIC
INPUT
0V
SWITCH
OUTPUT
VOUT
0V
tr < 20ns
tf < 20ns
tBBM
80%
C
V+
LOGIC
INPUT
V+
C
V-
C
NO0-NO7
ADDA-C
COM
GND INH
VOUT
RL
300Ω
CL
35pF
FIGURE 3A. tBBM MEASUREMENT POINTS
Repeat test for other switches. CL includes fixture and stray
capacitance.
FIGURE 3B. tBBM TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
8
FN6416.3
April 13, 2009

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