ISL8501 Просмотр технического описания (PDF) - Intersil

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ISL8501

Triple Output Controller with 1A Standard Buck PWM and Dual LDOs

Intersil 

ISL8501

The compensation gain uses external impedance networks

ZFB and ZIN to provide a stable, high bandwidth (BW) overall

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45°.

Include worst case component variations when determining

phase margin.

A more detailed explanation of voltage mode control of a

buck regulator can be found in Tech Brief TB417, titled

“Designing Stable Compensation Networks for Single Phase

Voltage Mode Buck Regulators.”

100

fZ1 fZ2 fP1 fP2

80

OPEN LOOP

60

ERROR AMP GAIN

40

20LOG

20 (R2/R1)

20LOG

0

(VIN/ΔVOSC)

MODULATOR

-20

GAIN

-40

-60

fLC

fESR

10 100 1k 10k 100k

COMPENSATION

GAIN

CLOSED LOOP

GAIN

1M 10M

FREQUENCY (Hz)

FIGURE 33. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

Layout Considerations

Layout is very important in high frequency switching

converter design. With power devices switching efficiently at

500kHz, the resulting current transitions from one device to

another cause voltage spikes across the interconnecting

impedances and parasitic circuit elements. These voltage

spikes can degrade efficiency, radiate noise into the circuit,

and lead to device overvoltage stress. Careful component

layout and printed circuit board design minimizes these

voltage spikes.

As an example, consider the turn-off transition of the upper

MOSFET. Prior to turn-off, the MOSFET is carrying the full

load current. During turn-off, current stops flowing in the

MOSFET and is picked up by the Schottky diode. Any

parasitic inductance in the switched current path generates a

large voltage spike during the switching interval. Careful

component selection, tight layout of the critical components,

and short, wide traces minimizes the magnitude of voltage

spikes.

There are two sets of critical components in the ISL8501

switching converter. The switching components are the most

critical because they switch large amounts of energy, and

therefore tend to generate large amounts of noise. Next are

the small signal components, which connect to sensitive

nodes or supply critical bypass current and signal coupling.

A multi-layer printed circuit board is recommended. Figure 34

shows the connections of the critical components in the

converter. Note that capacitors CIN and COUT could each

represent numerous physical capacitors. Dedicate one solid

layer (usually a middle layer of the PC board) for a ground

plane and make all critical component ground connections

with vias to this layer. Dedicate another solid layer as a

power plane and break this plane into smaller islands of

common voltage levels. Keep the metal runs from the

PHASE terminals to the output inductor short. The power

plane should support the input power and output power

nodes. Use copper filled polygons on the top and bottom

circuit layers for the phase nodes. Use the remaining printed

circuit layers for small signal wiring.

In order to dissipate heat generated by the internal LDO and

MOSFET, the ground pad, pin 29, should be connected to

the internal ground plane through at least four vias. This

allows the heat to move away from the IC and also ties the

pad to the ground plane through a low impedance path.

The switching components should be placed close to the

ISL8501 first. Minimize the length of the connections

between the input capacitors, CIN, and the power switches

by placing them nearby. Position both the ceramic and bulk

input capacitors as close to the upper MOSFET drain as

possible. Position the output inductor and output capacitors

between the upper and lower MOSFETs and the load.

The critical small signal components include any bypass

capacitors, feedback components, and compensation

components. Place the PWM converter compensation

components close to the FB and COMP pins. The feedback

resistors should be located as close as possible to the FB

pin with vias tied straight to the ground plane as required.

5V

PVCC

VIN

CBP1

ISL8501

RBP

VCC

CBP2

PHASE

PGND

VIN

D

CIN

L

COUT1

VOUT1

COMP

FB

C2

R2

C1

R1

R4

C3 R3

GND PAD

KEY

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER

VIA CONNECTION TO GROUND PLANE

FIGURE 34. PRINTED CIRCUIT BOARD POWER PLANES

AND ISLANDS

18

FN6500.1

July 12, 2007

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