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ISL84524 Просмотр технического описания (PDF) - Intersil

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ISL84524 Datasheet PDF : 12 Pages
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Test Circuits and Waveforms
ISL84524, ISL84525
C
V+
C
3V
LOGIC
INPUT
0V
SWITCH
OUTPUT 0V
tOFF
50%
tON
90% VOUT
tr < 20ns
tf < 20ns
90%
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. INHIBIT MEASUREMENT POINTS
V+
LOGIC
INPUT
C
NO0
ISL84524
NO1-NO3
COM
INH
ADD1,
GND ADD2
VOUT
RL
300
CL
35pF
V+
C
V+
LOGIC
INPUT
NC
ISL84525
NO
COM
INH
GND ADD
VOUT
RL
300
CL
35pF
Repeat test for other switches. CL includes fixture and stray
capacitance.
VOUT
=
V(NO or NC)
------------R-----L-------------
RL + R(ON)
FIGURE 1B. INHIBIT TEST CIRCUIT
V+
C
C
3V
LOGIC
INPUT
0V
SWITCH
OUTPUT
0V
50%
tTRANS
90% VOUT
tr < 20ns
tf < 20ns
90%
tTRANS
V+
LOGIC
INPUT
C
V+
LOGIC
INPUT
NO0
ISL84524
NO1-NO3
COM
ADD1
ADD2 GND INH
VOUT
RL
300
CL
35pF
V+
C
NC
NO
ADD
ISL84525
COM
GND INH
VOUT
RL
300
CL
35pF
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for other switches. CL includes fixture and stray
capacitance.
VOUT
=
V(NO or NC)
------------R-----L-------------
RL + R(ON)
FIGURE 1C. ADDRESS MEASUREMENT POINTS
FIGURE 1D. ADDRESS TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
6

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