IS93C56-3 Просмотр технического описания (PDF) - Integrated Silicon Solution

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IS93C56-3

2,048-BIT SERIAL ELECTRICALLY ERASABLE PROM

Integrated Silicon Solution 

IS93C56-3

FIGURE 7. WRITE DISABLE (WDS) CYCLE TIMING

tCS

CS

SK

DIN

10

0

00

DOUT = 3-STATE

ISSI ®

FIGURE 8. ERASE (REGISTER ERASE) CYCLE TIMING

SK

tCS

CS

DIN

1

1

1

X A6

DOUT

X is a don't care bit

A0

tSV

tDF

BUSY

tWP

READY

FIGURE 9. ERASE ALL (ERAL) CYCLE TIMING

SK

tCS

CS

DIN

DOUT

1

00

1

0

tSV

tDF

BUSY

tWP

READY

Note for Figures 8 and 9:

After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT

indicates BUSY status) then performs another instruction would cause device malfunction.

Integrated Silicon Solution, Inc. — 1-800-379-4774

9

Rev. G

04/26/01

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