IS62LV256AL(2006) Просмотр технического описания (PDF) - Integrated Silicon Solution

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IS62LV256AL
(Rev.:2006)

32K x 8 LOW VOLTAGE CMOS STATIC RAM

Integrated Silicon Solution 

IS65LV256AL

IS62LV256AL

WRITE CYCLE NO. 2 (CE Controlled)(1,2)

ADDRESS

CE

WE

DOUT

DIN

tWC

tSA

tSCE

tHA

tAW

tPWE

tHZWE

DATA UNDEFINED

HIGH-Z

tLZWE

tSD

tHD

DATA-IN VALID

ISSI ®

Notes:

1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if OE ≥ VIH.

8

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. A

03/17/06

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