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IS61SP25616

256K x 16, 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM

Integrated Silicon Solution 

IS61SP25616

IS61SP25618

ISSI ®

WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)

Symbol Parameter

-166

-150

-133

-5

Min. Max.

Min. Max.

Min. Max.

Min. Max.

Unit

tKC(1)

Cycle Time

6

—

6.7 —

7.5 —

10 —

ns

tKH(1)

Clock High Time

2.4 —

2.6 —

2.8 —

4

—

ns

tKL(1)

Clock Low Time

2.4 —

2.6 —

2.8 —

4

—

ns

tAS(1)

Address Setup Time

2

—

2

—

2

—

2

—

ns

tSS(1)

Address Status Setup Time

2

—

2

—

2

—

2

—

ns

tWS(1)

Write Setup Time

2

—

2

—

2

—

2

—

ns

tDS(1)

Data In Setup Time

2

—

2

—

2

—

2

—

ns

tCES(1)

Chip Enable Setup Time

2

—

2

—

2

—

2

—

ns

tAVS(1)

Address Advance Setup Time 2

—

2

—

2

—

2

—

ns

tAH(1)

Address Hold Time

0.5 —

0.5 —

0.5 —

0.5 —

ns

tSH(1)

Address Status Hold Time

0.5 —

0.5 —

0.5 —

0.5 —

ns

tDH(1)

Data In Hold Time

0.5 —

0.5 —

0.5 —

0.5 —

ns

tWH(1)

Write Hold Time

0.5 —

0.5 —

0.5 —

0.5 —

ns

tCEH(1)

Chip Enable Hold Time

0.5 —

0.5 —

0.5 —

0.5 —

ns

tAVH(1)

Address Advance Hold Time

0.5 —

0.5 —

0.5 —

0.5 —

ns

Note:

1. Tested with load in Figure 1.

Integrated Silicon Solution, Inc. — 1-800-379-4774

11

Rev. A

04/17/01

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