IS61NVP12836A-200B2I Просмотр технического описания (PDF) - Integrated Silicon Solution

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IS61NVP12836A-200B2I

128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

Integrated Silicon Solution 

IS61NLP12832A

IS61NLP12836A/IS61NVP12836A

IS61NLP25618A/IS61NVP25618A

BLOCK DIAGRAM

ISSI ®

x 32/x 36: A [0:16] or ADDRESS

x 18: A [0:17]

REGISTER

A2-A16 or A2-A17

MODE

A0-A1

BURST

ADDRESS

COUNTER

A'0-A'1

128Kx32;

128Kx36;

256Kx18

MEMORY ARRAY

K DATA-IN

REGISTER

CLK

CONTROL

CKE

LOGIC K

CE

CE2

CE2

} ADV

WE

BWŸX

(X=a,b,c,d or a,b)

OE

ZZ

CONTROL

REGISTER

DQx/DQPx

WRITE

ADDRESS

REGISTER

WRITE

ADDRESS

REGISTER

K DATA-IN

REGISTER

CONTROL

LOGIC

32, 36 or 18

K OUTPUT

REGISTER

BUFFER

2

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. 00C

09/12/05

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