IS61LV6432(1998) Просмотр технического описания (PDF) - Integrated Circuit Solution Inc
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IS61LV6432 Datasheet PDF : 16 Pages
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IS61LV6432
ISSI ®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter
-166
-133
-117
-5
-6
-7
-8
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC
Cycle Time
6 — 7.5 — 8.5 — 10 — 12 — 13 — 15 — ns
tKH
Clock High Time
2.4 — 2.8 — 3.0 — 3.5 — 4 — 6 — 6 — ns
tKL
Clock Low Time
2.4 — 2.8 — 3.0 — 3.5 — 4 — 6 — 6 — ns
tKQ
Clock Access Time
— 5 — 5 — 5 — 5 — 6 — 7 — 8 ns
tKQX(2) Clock High to Output Invalid 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 2 — 2 — ns
tKQLZ(2,3) Clock High to Output Low-Z
0—
0—
0—
0—
0—
0—
0 — ns
tKQHZ(2,3) Clock High to Output High-Z 1.5 5 1.5 5 1.5 6 1.5 6 1.5 6
26
26
ns
tOEQ Output Enable to Output Valid — 5 — 5 — 5 — 5 — 6 — 6 — 6 ns
tOEQX(2) Output Disable to Output Invalid 0 — 0 — 0 — 0 — 0 — 0 — 0 — ns
tOELZ(2,3) Output Enable to Output Low-Z 0 —
0—
0—
0—
0—
0—
0 — ns
tOEHZ(2,3) Output Disable to Output High-Z — 3
—3
—4
—4
—5
—6
—6
ns
tAS
Address Setup Time
2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tSS
Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tWS
Write Setup Time
2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tCES
Chip Enable Setup Time
2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tAH
Address Hold Time
0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH
Address Status Hold Time
0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tWH
Write Hold Time
0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH
Chip Enable Hold Time
0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tCFG
Configuration Setup(1)
2.5 — 30 — 35 — 35 — 45 — 52 — 60 — ns
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
12
Integrated Silicon Solution, Inc.
PRELIMINARY SR018-1C
06/01/98
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