IS61LV2568-10KI_03 Просмотр технического описания (PDF) - Integrated Silicon Solution
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IS61LV2568-10KI_03 Datasheet PDF : 9 Pages
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IS61LV2568
ISSI ®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol Parameter
-10 ns
-12 ns
Min. Max.
Min. Max.
Unit
tWC Write Cycle Time
tSCE CE to Write End
10 —
12 —
ns
8
—
9—
ns
tAW Address Setup Time to
Write End
8
—
9—
ns
tHA Address Hold from
Write End
0
—
0—
ns
tSA Address Setup Time
0
—
0—
ns
tPWE1 WE Pulse Width (OE = HIGH)
7
—
8—
ns
tPWE2 WE Pulse Width (OE = LOW)
8
—
10 —
ns
tSD Data Setup to Write End
5
—
6—
ns
tHD Data Hold from Write End
0
—
0—
ns
tHZWE(3) WE LOW to High-Z Output
—
4
—5
ns
tLZWE(3) WE HIGH to Low-Z Output
0
—
0—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to
3.0V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a
Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t WC
ADDRESS
CE
WE
DOUT
VALID ADDRESS
t SA
t SCE
DATA UNDEFINED
t AW
t PWE1
t PWE2
t HZWE
HIGH-Z
t HA
t LZWE
t SD
t HD
DIN
DATAIN VALID
CE_WR1.eps
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. B
02/07/03
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