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IRU1030

3A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR

International Rectifier 

IRU1030

V ESR

V ESL

T

LOAD

CURRENT

VC

1030plt1-1.0

LOAD CURRENT RISE TIME

Figure 5 - Typical regulator response to

the fast load current step.

An example of a regulator design to meet the Intel

Pentium Pro GTL+ specification is given below.

2) With the output capacitance being 1500mF:

DVc

=

Dt

3

C

DI

=

2

3 2.7

1500

=

3.6mV

Where:

Dt = 2ms is the regulator response time

To set the output DC voltage, we need to select R1 and

R2:

3) Assuming R1 = 121V, 0.5%:

( ) ( ) R2 =

VOUT

VREF

-1

3R1 =

1.5 -1

1.25

3121 = 24.2V

Select R2 = 24.3V, 0.5%

Assume the specification for the processor as shown in

Table 1:

Type of

VOUT

Processor Nominal

Pentium Pro 1.50 V

IMAX

Max Allowed

Output Tolerance

2.7 A

±150 mV

Table 1 - GTL+ Specification for Pentium Pro

The first step is to select the voltage step allowed in the

output due to the output capacitor’s ESR:

1) Assuming the regulator’s initial accuracy plus the re-

sistor divider tolerance is ≈ ±30mV (±2% of 1.5V nomi-

nal), then the total step allowed for the ESR and the

ESL, is −120 mV.

Assuming that the ESL drop is −10mV, the remain-

ing ESR step will be −110mV. Therefore the output

capacitor ESR must be:

ESR [ 110 = 40mV

2.7

The Sanyo MVGX series is a good choice to achieve

both price and performance goals. The 6MV1500GX,

1500mF, 6.3V has an ESR of less than 36mV typ.

Selecting a single capacitor achieves our design goal.

Selecting both R1 and R2 resistors to be 0.5% toler-

ance, results in the least amount of error introduced

by the resistor dividers leaving ≈ ±1.3% error budget

for the IRU1030 reference which is within the initial

accuracy of the device.

Finally, the input capacitor is selected as follows:

4) Assuming that the input voltage can drop 150mV be-

fore the main power supply responds, and that the

main power supply response time is ≈ 50ms, then

the minimum input capacitance for a 2.7A load step

is given by:

CIN

=

2.7 3 50

0.15

=

900mF

The ESR should be less than:

(VIN - VOUT - DV - VDROP)

ESR =

DI

Where:

VDROP L Input voltage drop allowed in step 4

DV L Maximum regulator dropout voltage

DI L Load current step

(3.3 - 1.5 - 1.2 - 0.15)

ESR =

= 0.16V

2.7

The next step is to calculate the drop due to the ca-

pacitance discharge and make sure that this drop in

voltage is less than the selected ESL drop in the

previous step.

Selecting a single 1500mF the same type as the output

capacitors exceeds our requirements. However, the same

input capacitor can also support the second regulator

for the other end of termination.

6

www.irf.com

Rev. 1.3

08/20/02

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