MT4LC4M4E9TG-5 Просмотр технического описания (PDF) - Micron Technology

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MT4LC4M4E9TG-5

4 MEG x 4 EDO DRAM

Micron Technology 

TECHNOLOGY, INC.

4 MEG x 4

EDO DRAM

Figure 1). WE# can also perform the function of disabling

the output devices under certain conditions, as shown in

Figure 2.

During an application, if the DQ outputs are wire OR’d,

OE# must be used to disable idle banks of DRAMs. Alter-

natively, pulsing WE# to the idle banks during CAS# high

time will also High-Z the outputs. Independent of OE#

control, the outputs will disable after tOFF, which is refer-

enced from the rising edge of RAS# or CAS#, whichever

occurs last.

REFRESH

Preserve correct memory cell data by maintaining power

and executing any RAS# cycle (READ, WRITE) or RAS#

refresh cycle (RAS#-ONLY, CBR or HIDDEN) so that all

combinations of RAS# addresses (2,048 for 2K and 4,096 for

4K) are executed within tREF (MAX), regardless of se-

quence. The CBR and Self Refresh cycles will invoke the

internal refresh counter for automatic RAS# addressing.

An optional Self Refresh mode is also available on the S

version. The “S” option allows the user the choice of a fully

static, low-power data retention mode or a dynamic refresh

mode at the extended refresh period of 128ms. The optional

Self Refresh feature is initiated by performing a CBR Re-

fresh cycle and holding RAS# LOW for the specified tRASS.

Additionally, the “S” option allows for an extended refresh

period of 128ms, or 31.25µs per row for a 4K refresh and

62.5µs per row for a 2K refresh if using distributed CBR

Refresh. This refresh rate can be applied during normal

operation, as well as during a standby or BATTERY BACKUP

mode.

The Self Refresh mode is terminated by driving RAS#

HIGH for a minimum time of tRPS. This delay allows for the

completion of any internal refresh cycles that may be in

process at the time of the RAS# LOW-to-HIGH transition.

If the DRAM controller uses a distributed refresh se-

quence, a burst refresh is not required upon exiting

Self Refresh. However, if the DRAM controller utilizes a

RAS#- ONLY or burst refresh sequence, all rows must be

refreshed within the average internal refresh rate, prior to

the resumption of normal operation.

STANDBY

Returning RAS# and CAS# HIGH terminates a memory

cycle and decreases chip current to a reduced standby level.

The chip is preconditioned for the next cycle during the

RAS# HIGH time.

RAS#

V

V

IH

IL

CAS#

V

V

IH

IL

,, ,,, ,,,,, ADDR

V IH

V IL

,,,,, , , DQ

V IOH

V IOL

ROW

COLUMN (A)

OPEN

VALID DATA (A)

t WHZ

WE#

V

V

IH

IL

tWPZ

OE#

V

V

IH

IL

,,,,,, ,,,,, COLUMN(B)

COLUMN (C)

,, ,,,,, VALIDDATA(B)

t WHZ

INPUT DATA (C)

COLUMN (D)

The DQs go to High-Z if WE# falls and, if tWPZ is met,

will remain High-Z until CAS# goes LOW with

WE# HIGH (i.e., until a READ cycle is initiated).

Figure 2

WE# CONTROL OF DQs

WE# may be used to disable the DQs to prepare

for input data in an EARLY WRITE cycle. The DQs

will remain High-Z until CAS# goes LOW with

WE# HIGH (i.e., until a READ cycle is initiated).

,,DON’T CARE

,,,,UNDEFINED

4 Meg x 4 EDO DRAM

D47.pm5 – Rev. 3/97

3

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©1997, Micron Technology, Inc.

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