HM62V16258BLTT-8 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HM62V16258BLTT-8

4 M SRAM (256-kword × 16-bit)

Hitachi -> Renesas Electronics 

HM62V16258B Series

Low VCC Data Retention Characteristics (Ta = 0 to +70°C)

Parameter

Symbol

Min Typ*4 Max Unit Test conditions*3

VCC for data retention

VDR

2.0 — — V

Vin ≥ 0V

(1) CS ≥ VCC – 0.2 V or

(2) LB = UB ≥ VCC – 0.2 V

CS ≤ 0.2 V

Data retention current

I *1

CCDR

— 0.8 20 µA VCC = 3.0 V, Vin ≥ 0V

(1) CS ≥ VCC – 0.2 V or

(2) LB = UB ≥ VCC – 0.2 V

CS ≤ 0.2 V

Chip deselect to data

retention time

I *2

CCDR

t CDR

— 0.8 10 µA

0 — — ns See retention waveform

Operation recovery time

tR

t *5

RC

—

—

ns

Notes: 1. This characteristic is guaranteed only for L-version, 10 µA max. at Ta = 0 to +40°C.

2. This characteristic is guaranteed only for L-SL version, 5 µA max. at Ta = 0 to +40°C.

3. CS controls address buffer, WE buffer, OE buffer, LB, UB buffer and Din buffer. If CS controls data

retention mode, Vin levels (address, WE, OE, LB, UB, I/O) can be in the high impedance state. If

LB, UB controls data retention mode, LB, UB must be LB = UB ≥ VCC – 0.2 V, CS must be CS ≤ 0.2

V. The other input levels (address, WE, OE, I/O) can be in the high impedance state.

4. Typical values are at VCC = 3.0 V, Ta = +25˚C and not guaranteed.

5. tRC = read cycle time.

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