HM62W16258BLTTI-7 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HM62W16258BLTTI-7

4 M SRAM (256-kword × 16-bit)

Hitachi -> Renesas Electronics 

HM62W16258BI Series

Low VCC Data Retention Characteristics (Ta = –40 to +85°C)

Parameter

Symbol

Min Typ*3 Max Unit Test conditions*2

VCC for data retention

VDR

2.0 — — V

Vin ≥ 0V

(1) CS ≥ VCC – 0.2 V or

(2) LB = UB ≥ VCC – 0.2 V

CS ≤ 0.2 V

Data retention current

I *1

CCDR

— 0.8 20 µA VCC = 3.0 V, Vin ≥ 0V

(1) CS ≥ VCC – 0.2 V or

(2) LB = UB ≥ VCC – 0.2 V

CS ≤ 0.2 V

Chip deselect to data

t CDR

retention time

0 — — ns See retention waveform

Operation recovery time

tR

t *4

RC

—

—

ns

Notes: 1. 10 µA max. at Ta = 0 to +40°C.

2. CS controls address buffer, WE buffer, OE buffer, LB, UB buffer and Din buffer. If CS controls data

retention mode, Vin levels (address, WE, OE, LB, UB, I/O) can be in the high impedance state. If

LB, UB controls data retention mode, LB, UB must be LB = UB ≥ VCC – 0.2 V, CS must be CS ≤ 0.2

V. The other input levels (address, WE, OE, I/O) can be in the high impedance state.

3. Typical values are at VCC = 3.0 V, Ta = +25˚C and not guaranteed.

4. tRC = read cycle time.

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