HM62W16255HCLJP-10 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics
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HM62W16255HCLJP-10 Datasheet PDF : 18 Pages
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HM62W16255HC Series
Write Cycle
HM62W16255HC
-10
Parameter
Symbol
Min
Max
Unit
Notes
Write cycle time
t WC
10
—
ns
Address valid to end of write
t AW
7
—
ns
Chip select to end of write
t CW
7
—
ns
8
Write pulse width
t WP
7
—
ns
7
Byte select to end of write
tLBW, tUBW
7
—
ns
9, 10
Address setup time
t AS
0
—
ns
5
Write recovery time
t WR
0
—
ns
6
Data to write time overlap
t DW
5
—
ns
Data hold from write time
t DH
0
—
ns
Write disable to output in low-Z
t OW
3
—
ns
1
Output disable to output in high-Z
t OHZ
—
5
ns
1
Write enable to output in high-Z
t WHZ
—
5
ns
1
Notes: 1. Transition is measured ±200 mV from steady voltage with Load (B). This parameter is sampled
and not 100% tested.
2. If the CS or LB or UB low transition occurs simultaneously with the WE low transition or after the
WE transition, output remains a high impedance state.
3. WE and/or CS must be high during address transition time.
4. If CS, OE, LB and UB are low during this period, I/O pins are in the output state. Then the data
input signals of opposite phase to the outputs must not be applied to them.
5. tAS is measured from the latest address transition to the latest of CS, WE, LB or UB going low.
6. tWR is measured from the earliest of CS, WE, LB or UB going high to the first address transition.
7. A write occurs during the overlap of low CS, low WE and low LB or low UB.
8. tCW is measured from the later of CS going low to the end of write.
9. tLBW is measured from the later of LB going low to the end of write.
10. tUBW is measured from the later of UB going low to the end of write.
9
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