IDT82P20516 Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

Список матч

IDT82P20516

16-Channel Short Haul E1 Line Interface Unit

Integrated Device Technology 

List of Figures

Figure-1 Functional Block Diagram ............................................................................................................................................................................ 10

Figure-2 484-Pin Fine Pitch BGA (Top View) ............................................................................................................................................................. 11

Figure-3 Switch between Impedance Matching Modes .............................................................................................................................................. 19

Figure-4 Receive Differential Line Interface with Twisted Pair Cable (with transformer) ........................................................................................... 20

Figure-5 Receive Differential Line Interface with Coaxial Cable (with transformer) ................................................................................................... 20

Figure-6 Receive Differential Line Interface with Twisted Pair Cable (transformer-less, non standard compliant) .................................................... 20

Figure-7 Receive Path Monitoring .............................................................................................................................................................................. 21

Figure-8 Transmit Path Monitoring ............................................................................................................................................................................. 21

Figure-9 E1 Waveform Template ............................................................................................................................................................................... 24

Figure-10 E1 Waveform Template Measurement Circuit ............................................................................................................................................ 24

Figure-11 Transmit Differential Line Interface with Twisted Pair Cable (with Transformer) ........................................................................................ 28

Figure-12 Transmit Differential Line Interface with Coaxial Cable (with transformer) ................................................................................................. 28

Figure-13 Transmit Differential Line Interface with Twisted Pair Cable (transformer-less, non standard compliant) .................................................. 28

Figure-14 Jitter Attenuator ........................................................................................................................................................................................... 30

Figure-15 LLOS Indication on Pins .............................................................................................................................................................................. 32

Figure-16 TLOS Detection Between Two Channels .................................................................................................................................................... 34

Figure-17 Pattern Generation (1) ................................................................................................................................................................................. 36

Figure-18 Pattern Generation (2) ................................................................................................................................................................................. 36

Figure-19 PRBS / ARB Detection ................................................................................................................................................................................ 37

Figure-20 IB Detection ................................................................................................................................................................................................. 38

Figure-21 Automatic Error Counter Updating .............................................................................................................................................................. 39

Figure-22 Manual Error Counter Updating .................................................................................................................................................................. 39

Figure-23 Priority Of Diagnostic Facilities During Analog Loopback ........................................................................................................................... 40

Figure-24 Priority Of Diagnostic Facilities During Manual Remote Loopback ............................................................................................................. 41

Figure-25 Priority Of Diagnostic Facilities During Digital Loopback ............................................................................................................................ 42

Figure-26 G.772 Monitoring ......................................................................................................................................................................................... 43

Figure-27 Automatic JM Updating ............................................................................................................................................................................... 44

Figure-28 Manual JM Updating ................................................................................................................................................................................... 44

Figure-29 Interrupt Service Process ............................................................................................................................................................................ 48

Figure-30 Reset ........................................................................................................................................................................................................... 49

Figure-31 1+1 HPS Scheme, Differential Interface (Shared Common Transformer) .................................................................................................. 51

Figure-32 1:1 HPS Scheme, Differential Interface (Individual Transformer) ............................................................................................................... 52

Figure-33 1+1 HPS Scheme, E1 75 ohm Single-Ended Interface (Shared Common Transformer) ........................................................................... 53

Figure-34 JTAG Architecture ....................................................................................................................................................................................... 92

Figure-35 JTAG State Diagram ................................................................................................................................................................................... 93

Figure-36 Transmit Clock Timing Diagram ................................................................................................................................................................ 104

Figure-37 Receive Clock Timing Diagram ................................................................................................................................................................. 104

Figure-38 CLKE1 Clock Timing Diagram ................................................................................................................................................................... 105

Figure-39 E1 Jitter Tolerance Performance ............................................................................................................................................................... 106

Figure-40 E1 Jitter Transfer Performance ................................................................................................................................................................. 107

Figure-41 Read Operation in Serial Microprocessor Interface .................................................................................................................................. 108

Figure-42 Write Operation in Serial Microprocessor Interface ................................................................................................................................... 108

Figure-43 Timing Diagram ......................................................................................................................................................................................... 109

Figure-44 JTAG Timing ............................................................................................................................................................................................. 110

List of Figures

7

December 17, 2009

Share Link: