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IDT82V3395 Просмотр технического описания (PDF) - Integrated Device Technology

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IDT82V3395
IDT
Integrated Device Technology IDT
IDT82V3395 Datasheet PDF : 5 Pages
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IDT82V3395 PRODUCT BRIEF
DUAL SYNCHRONOUS ETHERNET LINE CARD PLL
DESCRIPTION
The IDT82V3395 is an integrated, single-chip solution for the Syn-
chronous Equipment Timing applications in SONET / SDH / Synchro-
nous Ethernet equipment, DWDM and Wireless base station.
The device supports several types of input clock sources: recovered
clock from Synchronous Ethernet, STM-N or OC-n, PDH network syn-
chronization timing.
The device consists of 2 DPLL+APLL paths. The two path lock inde-
pendently from each other.
An input clock is automatically or manually selected for both path.
Both paths support three primary operating modes: Free-Run, Locked
and Holdover. In Free-Run mode, the DPLL refers to the master clock.
In Locked mode, the DPLL locks to the selected input clock. In Holdover
mode, the DPLL resorts to the frequency data acquired in Locked mode.
Whatever the operating mode is, the DPLL gives a stable performance
without being affected by operating conditions or silicon process varia-
tions.
There are 2 high performance APLLs that can be used for low jitter
SONET and Ethernet Clocks
The device provides programmable DPLL bandwidths: 18 Hz, 35 Hz,
70 Hz and 560 Hz.
A stable input is required for the master clock in different applica-
tions. The master clock is used as a reference clock for all the internal
circuits in the device.
All the read/write registers are accessed through a microprocessor
interface. The device supports I2C and serial microprocessor interface
modes.
Description
2
March 5, 2012

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