IDT82V3001A(2008) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT82V3001A
(Rev.:2008)

WAN PLL WITH SINGLE REFERENCE INPUT

Integrated Device Technology 

LIST OF FIGURES

Figure - 1

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Block Diagram .................................................................................................................................................. 2

IDT82V3001A SSOP56 Package Pin Assignment........................................................................................... 6

State Control Block......................................................................................................................................... 10

State Control Diagram.................................................................................................................................... 11

TIE Control Circuit Diagram ........................................................................................................................... 12

State Switch with TIE Control Block Enabled................................................................................................. 13

State Switch with TIE Control Block Disabled ................................................................................................ 13

DPLL Block Diagram ...................................................................................................................................... 14

Clock Oscillator Circuit ................................................................................................................................... 15

Power-Up Reset Circuit.................................................................................................................................. 15

IDT82V3001A Power Decoupling Scheme .................................................................................................... 16

Input to Output Timing (Normal Mode)........................................................................................................... 25

Output Timing 1.............................................................................................................................................. 26

Output Timing 2.............................................................................................................................................. 27

Input Control Setup and Hold Timing ............................................................................................................. 27

List of Figures

4

October 15, 2008

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