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IDTCV152

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

Integrated Device Technology 

IDTCV152

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

COMMERCIAL TEMPERATURE RANGE

ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT

PARAMETERS

Following Conditions Apply Unless Otherwise Specified:

Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%

Symbol

VIH

VIL

VIH_FS

VIL_FS

IIL

IDD3.3OP

IDD3.3PD

Parameter

Input HIGH Voltage

Input LOW Voltage

LOW Voltage, HIGH Threshold

LOW Voltage, LOW Threshold

Input LeakageCurrent

Operating Supply Current

Powerdown Current

FI

LPIN

CIN

COUT

CINX

TSTAB

Input Frequency(1)

Pin Inductance(2)

Input Capacitance(2)

Clock Stabilization(2,3)

Modulation Frequency(2)

TDRIVE_PD(2)

TFALL_PD(2)

TRISE_PD(2)

Test Conditions

3.3V ± 5%

3.3V ± 5%

For FSA.B.C test_mode

For FSA.B.C test_mode

0< VIN < VDD, no internal pull-up or pull-down

Full active, CL = full load

All differential pairs driven

All differential pairs tri-stated

VDD = 3.3V

Logic inputs

Output pin capacitance

XTAL_IN and XTAL_OUT pins

From VDD power-up or de-assertion of PD to first clock

Triangular modulation

CPU output enable after PD de-assertion

Fall time of PD

Rise time of PD

Min. Typ.

Max.

Unit

2

—

VDD + 0.3

V

VSS - 0.3 —

0.8

V

0.7

—

VDD + 0.3

V

VSS - 0.3 —

0.35

V

–5

—

+5

mA

—

—

400

mA

—

—

70

mA

—

—

12

— 14.31818 —

MHz

—

—

7

nH

—

—

5

—

—

6

pF

—

—

5

—

—

1.8

ms

30

—

33

KHz

—

—

300

us

—

—

5

ns

—

—

5

ns

NOTES:

1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.

2. This parameter is guaranteed by design, but not 100% production tested.

3. See TIMING DIAGRAMS for timing requirements.

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