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IDTCV107E

CLOCK GENERATOR FOR DESKTOP PC PLATFORMS

Integrated Device Technology 

IDTCV107E

CLOCK GENERATOR FOR DESKTOP PC PLATFORMS

COMMERCIAL TEMPERATURE RANGE

ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT

PARAMETERS

Following Conditions Apply Unless Otherwise Specified:

Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

VIH

VIL

IIH

IIL1

IIL2

IDD3.3OP

IDD3.3PD

3.3V Input HIGH Voltage

3.3V Input LOW Voltage

Input HIGH Current

Input LOW Current

Input LOW Current

Operating Supply Current

Powerdown Current

FI

LPIN

CIN

COUT

CINX

TSTAB

Input Frequency(2)

Pin Inductance(3)

Input Capacitance(3)

Clock Stabilization(3,4)

Modulation Frequency(3)

TDRIVE_SRC(3)

TDRIVE_PD#(3)

TFALL_PD#(3)

TRISE_PD#(4)

TDRIVE_CPU_Stop#(3)

TFALL_CPU_Stop#(3)

TRISE_CPU_Stop#(4)

3.3V ± 5%

3.3V ± 5%

VIN = VDD

VIN = 0V, inputs with no pull-up resistors

VIN = 0V, inputs with pull-up resistors –200

Full active, CL = full load

All differential pairs driven

All differential pairs tri-stated

VDD = 3.3V

Logic inputs

Output pin capacitance

X1 and X2 pins

From VDD power-up or de-assertion of PD# to first clock

Triangular modulation

SRC output enable after PCI_Stop# de-assertion

CPU output enable after PD# de-assertion

Fall time of PD#

Rise time of PD#

CPU output enable after CPU_Stop# de-assertion

Fall time of PD#

Rise time of PD#

2

—

VDD + 0.3

V

VSS - 0.3

—

–5

—

0.8

V

5

µA

–5

—

—

µA

—

—

µA

—

—

400

mA

—

—

70

mA

—

—

12

— 14.31818 —

MHz

—

—

7

nH

—

—

5

—

—

6

pF

—

—

5

—

—

1.8

ms

30

—

33

KHz

—

—

15

ns

—

—

300

us

—

—

5

ns

—

—

5

ns

—

—

10

us

—

—

5

ns

—

—

5

ns

NOTES:

1. Available to CV104, CV105, CV107, and CV109.

2. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.

3. This parameter is guaranteed by design, but not 100% production tested.

4. See TIMING DIAGRAMS for timing requirements.

15

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