QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL
TEMPERATURE RANGES
3.3 RECEIVE PATH
The receive path consists of Receive Internal Termination, Monitor
Gain, Amplitude/Wave Shape Detector, Digital Tuning Controller, Adaptive
Equalizer, Data Slicer, CDR (Clock and Data Recovery), Optional Jitter
Attenuator, Decoder and LOS/AIS Detector. Refer to Figure-7.
3.3.1 RECEIVE INTERNAL TERMINATION
The impedance matching can be realized by the internal impedance
matching circuit or the external impedance matching circuit. If R_TERM[2]
is set to ‘0’, the internal impedance matching circuit will be selected. In this
case, the R_TERM[1:0] bits (TERM, 1AH...) can be set to choose 75 Ω, 100
Ω, 110 Ω or 120 Ω internal impedance of RTIPn/RRINGn. If R_TERM[2]
is set to ‘1’, the internal impedance matching circuit will be disabled. In this
case, the external impedance matching circuit will be used to realize the
impedance matching.
Figure-8 shows the appropriate external components to connect with
the cable for one channel. Table-15 is the list of the recommended imped-
ance matching for receiver.
LOS/AIS
Detector
LOS
RTIP
RRING
Receive
Internal
termination
Monitor Gain
Adaptive
Equalizer
Data Slicer
Clock
and Data
Recovery
Jitter
Attenuator
Decoder
RCLK
RDP
RDN
Figure-7 Receive Path Function Block Diagram
Table-15 Impedance Matching for Receiver
Cable Configuration
Internal Termination
R_TERM[2:0]
E1/75 Ω
000
E1/120 Ω
001
T1
010
J1
011
RR
120 Ω
External Termination
R_TERM[2:0]
1XX
RR
75 Ω
120 Ω
100 Ω
110 Ω
A
RX Line
B
TX Line
•1:1•
•2:1•
VDDRn
D8
•
•·
D7
RR VDDRn
D6
• D5 •· VDDTn
RT
D4
•·
D3
Cp2
VDDTn
D2
•·
RT
D13
One of the Four Identical Channels
RTIPn
VDDRn
RRINGn
TTIPn
GNDRn
VDDTn
TRINGn
GNDTn
0.1 F
•
0.1 F
•
Note: 1. Common decoupling capacitor
2. Cp 0-560 (pF)
3. D1 - D8, Motorola - MBR0540T1;
International Rectifier - 11DQ04 or 10BQ060
Figure-8 Transmit/Receive Line Circuit
3.3 V
68 F1
3.3 V
68 F1
20